UTE-R

The UTE-R has the following features including Up to 125,000 usable equivalent gates;QML Q and V compliant;Designed specifically for high reliability applications;Advanced sub-micron (0.9 lei) silicon gate CMOS process;JTAG (IEEE 1149.1) boundary-scan registers built into I/O cells;Low noise package technology for high-speed circuits;Latchup-immune over specified use conditions;Radiation-hardened to 1.0E6 rads(Si) total dose(functional) and SEU-immune cells to less than 1.0E-10 errors/bit-day (UTE-R process);Design support using Mentor Graphics), Synopsys and VHDL tools on HP and Sun workstations;Ability to translate/alternate source FPGAs and third-party ASIC designs;Approved by NASA for listing in MIL-STD-975;Available against Standard Microcircuit Drawing 5962-96B 02.

The high-performance UTE-R gate array family features densities of up to 125,000 equivalent gates and is available in MIL-PRF-38535 QML Q and V quality levels and radiation-hardened (UTE-R).The UTE-R processes feature submicron channel lengths (0.9 lei) in a twin-tub, epitaxial bulk CMOS technology. These processes have options for two or three levels of metal interconnect which allow efficient layouts for designs requiring high functional density.For those designs requiring stringent radiation hardness,special processing techniques are used to enhance the total dose radiation hardness of the field and gate oxides while maintaining circuit density and reliability. In addition, for both greater transient radiation hardness and latchup immunity, the radiation-hardened processes are built on epitaxial substrate wafers.Developed from UTMC's patented architectures, the UTE-R array family uses a highly efficient continuous-transistor architecture for the internal cell constructions. This arrangement minimizes the number of otherwise unusable transistors common in conventional Ulock-structured arrays.Combined with placement and routing tools, the utilization of available transistors is maximized using two or three levels of metal interconnect, enabling the designer to achieve very high functional density in a single ASIC.

UTE-R output drivers feature programmable slew rate control for minimizing noise and switching transients. This feature allows the user to optimize edge characteristics to match system requirements. Separate on-chip power and ground buses are provided for internal cells and output drivers which further isolate internal design circuitry from switching noise.Flatpacks are available with up to 304 leads;1'GAs are available with up to 280 leads. UTMC's flatpacks feature a non-conductive tie bar that helps maintain lead integrity through test and handling operations. In addition to the packages listed in table 2, UTMC offers custom package development and package tooling modification services for individual requirements.