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UTC3511

Features: · The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level.· The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level.· Both of the power good output (PGO) and the fault protection latch (FPL_N) are Open Drain Output.· 75 ms time delay for UVD.· 300 ms tim...

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SeekIC No. : 004539236 Detail

UTC3511: Features: · The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level.· The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level.· Both of the power good output (PGO) ...

UTC3511 Data Sheet

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Part Number:
UTC3511
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/13

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Product Details

Description



Features:

· The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level.
· The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level.
· Both of the power good output (PGO) and the fault protection latch (FPL_N) are Open Drain Output.
· 75 ms time delay for UVD.
· 300 ms time delay for PGO.
· 38 ms for PDON_N input signal De-bounce.
· 73 us for internal signal De-glitches.
· 2.4 ms time delay for PDON_N turn-off FPL_N.


Pinout

Connection Diagram


Specifications

PARAMETER SYMBOL RATINGS UNIT
Supply voltage VDD -0.3 ~ 16 V
Input Voltage PDON_N,V5,V33,PGI Vin -0.3 ~ 7 V
Output Voltage
FPL_N
PGO		 VOUT -0.3 ~ 16 V
-0.3 ~ 7
Operating temperature Topr -40 ~ 125
Storage temperature Tstg -55 ~ 150



Description

The UTC3511 provides protection circuits, power good output (PGO), fault protection latch (FPL_N), and protection detector function (PDON_N) control.

It can minimize external components of switching power supply systems in personal computer.

The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. When OVD or UVD detect the fault voltage level, the FPL_N is latched HIGH and PGO goes LOW. The latch can be reset by PDON_N going HIGH. There is 2.4ms delay time for PDON_N turning off FPL_N.

When OVD and UVD detect the right voltage level, the power good output (PGO) will be issue.




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