UT7C138

Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. Maximum junction temperature may be increased to +175 during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012, infinite heat sink.

The UT7C138 and UT7C139 are high-speed radiationhardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.

Arbitration schemes are included on the UT7C138/139 to handle situations when multiple processors access the same memory location. Two ports provide independent, asynchronous access for reads and writes to any location in memory. The UT7C138/139 can be utilized as a stand-alone 32/36-Kbit dual-port static RAM or multiple devices can be combined in order to function as a 16/18-bit or wider master/ slave dual-port static RAM. For applications that require depth expansion, theBUSY pin is open-collector allowing for wired OR circuit configuration. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications, and status buffering.

Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). BUSYsignals that the port is trying to access the same location currently being accessed by the other port.