UT71563C

The UT71563C has the following features including asynchronous operation for compatibility with industry-standard 32K*8 SRAM;TTL compatible input and output levels;Three-state bidirectional data bus;Low operating and standby current;Latchup immune.

The UT71563C SRAM is a high performance,asynchronous, radiation-hardened, 32K x 8 random access memory conforming to industry-standard fit, form,and function. The UT71563C SRAM features fully static operation requiring no external clocks or timing strobes.UTMC designed and implemented the UT71563C SRAM using an advanced radiation-hardened (EPI-CMOS) process and a device enable/disable function resulting in a high performance, power-saving SRAM. The combination of radiation-hardness, fastaccess time, and low power consumption makeUT71563C ideal for high-speed systems designed for operation in radiation environments.A combination ofWgreater than VIg(min),E1 less than Vll(max), and E2 greater than Vig(min) defines a read cycle. Read access time is measured from the latter of device enable, output enable, or valid address to valid data output.The UT71563V SRAM incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse.

Stresses outside the listed absolute ma}omum ratings may cause permanent damage to the device. This is a stress rating only,and functional operation of the UT71563C at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Read Cycle 3, the Output Enable-controlled Access in figure 3c, is initiated by G going active while E1 and E2 are asserted, W is deasserted, and the addresses are stable. Read access time is tGLQV unless tAVQV or tETQV have not been satisfied.