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UT54LVDS217

Features: ` 15 to 75 MHz shift clock support` Low power consumption` Power-down mode <216W (max)` Cold sparing all pins` Narrow bus reduces cable size and cost` Up to 1.575 Gbps throughput` Up to 197 Megabytes/sec bandwidth` 325 mV (typ) swing LVDS devices for low EMI` PLL requires no external ...

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UT54LVDS217: Features: ` 15 to 75 MHz shift clock support` Low power consumption` Power-down mode <216W (max)` Cold sparing all pins` Narrow bus reduces cable size and cost` Up to 1.575 Gbps throughput` Up to...

UT54LVDS217 Data Sheet

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Part Number:
UT54LVDS217
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

` 15 to 75 MHz shift clock support
` Low power consumption
` Power-down mode <216W (max)
` Cold sparing all pins
` Narrow bus reduces cable size and cost
` Up to 1.575 Gbps throughput
` Up to 197 Megabytes/sec bandwidth
` 325 mV (typ) swing LVDS devices for low EMI
` PLL requires no external components
` Rising edge strobe
` Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019
   - Total-dose: 300 krad(Si) and 1 Mrad(Si)
   - Latchup immune (LET > 100 MeV-cm2/mg)
` Packaging options:
   - 48-lead flatpack
` Standard Microcircuit Drawing 5962-01534
   - QML Q and V compliant part


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.3 to 4.0V
VI/O Voltage on any pin4 -0.3 to (VDD + 0.3V)
TSTG Storage temperature -65 to +150
PD Maximum power dissipation 2 W
TJ Maximum junction temperature2 +15
JC Thermal resistance, junction-to-case3 10/W
II DC input current ±10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and lifetest.
3. Test per MIL-STD-883, Method 1012.
4. For cold spare mode (VDD = VSS), VI/O may be 0.3V to the maximum recommended operating VDD + 0.3V.


Description

The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted.

At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel. Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec).

The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.

All pins of the UT54LVDS217 have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.




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