UT54LVDS032LV

The UT54LVDS032LV receiver's intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100W. A termination resistor of 100W should be selected to match the media and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The UT54LVDS032LV Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400.0 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The UT54LVDS032LV accepts low voltage (340mV) differential input signals and translates them to 3V CMOS output levels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (100 W) input fail-safe. Receiver output will be HIGH for all fail-safe conditions.

The UT54LVDS032LV and companion quad line driver UT54LVDS031LV provides new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications.

All pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS.