UT54LVDS032

Features:

·>155.5 Mbps (77.7 MHz) switching rates
·±340mV differential signaling
·5 V power supply
·TTL compatible outputs
·Ultra low power CMOS technology
·8.0ns maximum propagation delay
·3.0ns maximum differential skew
·Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019
      - Total-dose: 300 krad(Si) and 1Mrad(Si)
      - Latchup immune (LET > 111 M eV-cm2/mg)
·Packaging options:
      - 16-lead flatpack (dual in-line)
·Standard Microcircuit Drawing 5962-95834
      - QML Q and V compliant part
·Compatible with IEEE 1596.3SCI LVDS
·Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard


Pinout




Specifications

SYMBOL	PARAMETER	LIMITS
VDD	DC Supply Voltage	-0.3 to 6.0V
VI/O	Voltage on Any Pin	-0.3 to (VDD + 0.3V)
TSTG	Storage Temperature	-65 to +150
PD	Maximum Power Dissipation	1.25 W
TJ	Maximum Junction Temperature2	+150
JC	Thermal Resistance, Junction-to-Case 3	10/W
II	DC Input Current	±10mA

Description

The UT54LVDS032 Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The UT54LVDS032 accepts low voltage (340mV) differential input signals and translates them to 5V TTL output levels. The receiver supports a three-state function that may be used to multiplex outputs. The receiver also supports OPEN, shorted and terminated (100 W) input failsafe. Receiver output will be HIGH for all fail-safe conditions.

The UT54LVDS032 and companion quad line driver UT54LVDS031 provides new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications.