UT54ACTS220

1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the  operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The UT54ACTS220 is designed to be a companion chip to UTMC's UT69151 SMMIT family for the purpose of generating clock and wait-state signals. The device contains a divide by two circuit that accepts TTL input levels and drives CMOS output buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state circuit generates a single wait-state by delaying the falling edge of DTACK into the SMMIT. The clock/timing device generates DTACK from the falling edge of input RCS which is synchronized by the falling edge of 24MHz. The SMMIT of the UT54ACTS220 drives inputs RCS and DMACK