UT54ACTS109

Features:

• 1.2radiation-hardened CMOS
   - Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
   - 16-pin DIP
   - 16-lead flatpack






Pinout




Specifications

SYMBOL	PARAMETER	LIMIT	UNITS
VDD	Supply voltage	-0.3 to 7.0	V
VI/O	Voltage any pin	-.3 to VDD +.3	V
TSTG	Storage Temperature range	-65 to +150
TJ	Maximum junction temperature	+175
TLS	Lead temperature (soldering 5 seconds)	+300
JC	Thermal resistance junction to case	20	/W
II	DC input current	10	mA
PD	Maximum power dissipation	1	W

Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device.
This is a stress rating only, functional operation of the device at these or any other conditions beyond
limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.


Description

The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the J and K input can be changed without affecting the levels at the outputs. The flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D flip-flops if J and K are tied together.

The UT54ACTS109 are characterized over full military temperature range of -55 to +125.