Features: · High speed Universal RADPAL - tPD: 15.5ns, 20ns, 25ns maximum - fMAX1: 33MHz maximum external frequency - Supported by industry-standard programmer - Amorphous silicon anti-fuse· Asynchronous and synchronous RADPAL operation - Synchronous PRESET - Asynchronous RESET· Up to 22 input and...
UT22VP10: Features: · High speed Universal RADPAL - tPD: 15.5ns, 20ns, 25ns maximum - fMAX1: 33MHz maximum external frequency - Supported by industry-standard programmer - Amorphous silicon anti-fuse· Asynchr...
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Symbol |
Parameter |
LIMIT |
Unit |
VDD |
Supply voltage |
-0.3 to 7.0 |
V |
VI/O2 |
Input voltage any pin |
-0.3 to +7.0 |
V |
TSTG |
Storage Temperature range |
-65 to +150 |
|
TJ |
Maximum junction temperature |
+175 |
|
TS |
Lead temperature (soldering 10 seconds) |
+300 |
|
JC |
Thermal resistance junction to case |
20 |
/W |
II |
DC input current |
±10 |
mA |
PD3 |
Maximum power dissipation |
1.6 |
W |
IO |
Output sink current |
12 |
mA |
The UT22VP10 RADPAL is a fuse programmable logic array device. The familiar sum-of-products (AND-OR) logic structure is complemented with a programmable macrocell. The UT22VP10 is available in 24-pin DIP, 24-lead flatpack, and 28-lead quad-flatpack package offerings providing up to 22 inputs and 10 outputs. Amorphous silicon anti-fuse technology provides the programming of each output. The user specifies whether each of the potential outputs is registered or combinatorial. Output polarity is also individually selected, allowing for greater flexibility for output configuration. A unique output enable function allows the user to configure bidirectional I/O on an individual basis.
The UT22VP10 architecture implements variable sum terms providing 8 to 16 product terms to outputs. This feature provides the user with increased logic function flexibility. Other features include common synchronous preset and asynchronous reset. These features eliminate the need for performing the initialization function.
The UT22VP10 provides a device with the flexibility to implement logic functions in the 500 to 800 gate complexity. The flexible architecture supports the implementation of logic functions requiring up to 21 inputs and only a single output or down to 12 inputs and 10 outputs. Development and programming support for the UT22VP10 is provided by DATA I/O.