UPD720130

Features:

• Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
• Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
• USB2.0 high-speed bus powered device capability
• Certified by USB implementers forum and granted with USB 2.0 high-speed Logo (TID :40320125)
• One USB2.0 high-speed transceiver / receiver with full-speed transceiver / receiver
• USB2.0 High-speed or Full-speed packet protocol sequencer (Serial Interface Engine)
• Automatic chirp assertion and full-/high-speed mode change
• USB Reset, Suspend and Resume signaling detection
• Supports power control functionality for IDE device as CD-ROM and HDD
• Supports set feature (TEST_MODE) functionality
• System Clock is generated by 30 MHz X'tal
• 2.5 V and 3.3 V power supply


Pinout




Specifications

 

Parameter	Symbol	Condition	Rating	Unit
Power supply voltage	VDD33 VDD25	3.3 V power supply rail 2.5 V power supply rail	−0.5 to +4.6 −0.5 to +3.6	V V
Input voltage, 5 V buffer	VI	3.0 V < VDD33 < 3.6 V V I < VDD33 + 3.0 V	−0.5 to +6.6	V
Input voltage, 3.3 V buffer	VI	3.0 V < VDD33 < 3.6 V VI < VDD33 + 1.0 V	−0.5 to +4.6	V
Input voltage, 2.5 V buffer	VI	2.3 V VI < VDD25 + 0.9 V	−0.5 to +3.6	V
Output voltage, 5 V buffer	VO	3.0 V < VDD33 < 3.6 V VO < VDD33 + 3.0 V	−0.5 to +6.6	V
Output voltage, 3.3 V buffer	VO	3.0 V < VDD33 < 3.6 V VO < VDD33 + 1.0 V	−0.5 to +4.6	V
Output voltage, 2.5 V buffer	VO	2.3 V< VDD25 < 2.7 V VO < VDD25 + 0.9 V	−0.5 to +3.6	V
Output current, 5 V buffer	IO	IOL = 6 mA	20	mA
Output current, 3.3 V buffer	IO	IOL = 6 mA IOL = 3 mA	20 10	mA mA
Operating ambient temperature	TA		0 to +70
Storage temperature	Tstg		−65 to +150

Description

The µPD720130 is designed to perform a bridge between USB 2.0 and ATA/ATAPI.  The µPD720130 complieswith the Universal Serial Bus Specification Revision 2.0  full-/high-speed signaling and works up to 480 Mbps.  TheµPD720130is integrated CISC processor, ATA/ATAPI controller, endpoint controller (EPC), serial interface engine(SIE), and USB2.0 transceiver into a single chip.  The USB2.0 protocol and class specific protocol (bulk onlyprotocol) are handled by USB2.0 transceiver, SIE, and EPC.  And the transport layer is performed by V30MZ CISCprocessor which is in the µPD720130.  The software to control the µPD720130 is located in an embedded ROM. Inthe future, the µPD720130will be released to support external Flash Memory / EEPROM™ option to update functionby firmware.