Features: • 1.8 ± 0.1 V power supply and HSTL I/O• DLL circuitry for wide output data valid window and future frequency scaling• Pipelined double data rate operation• Common data input/output bus• Two-tick burst for low DDR transaction size• Two input clocks (K ...
UPD44324182: Features: • 1.8 ± 0.1 V power supply and HSTL I/O• DLL circuitry for wide output data valid window and future frequency scaling• Pipelined double data rate operation• Common ...
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DescriptionThe UPD42S16800L is designed as 2097152 wirds by 8 bits dynamic CMOS RAM with refresh c...
Features: • 131,072 words by 8 bits organization• Fast access time: 70, 85, 100, 120, ...
DescriptionThe UPD4364CX-10 is one member of the UPD4364 family which is designed as the 8192 x 8-...
Parameter | Symbol | Conditions | MIN. | TYP. | MAX. | Unit |
Supply voltage | VDD | 0.5 | +2.5 | V | ||
Output supply voltage | VDDQ | 0.5 | VDD | V | ||
Input voltage | VIN | 0.5 | VDD + 0.5 (2.5 V MAX.) | V | ||
Input / Output voltage | VI/O | 0.5 | VDDQ + 0.5 (2.5 V MAX.) | V | ||
Operating ambient temperature | TA | 0 | 70 | |||
Storage temperature | Tstg | 55 | +125 |
The µPD44324082 is a 4,194,304-word by 8-bit, the µPD44324092 is a 4,194,304-word by 9-bit, the UPD44324182 is a 2,097,152-word by 18-bit and the µPD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44324082, µPD44324092, UPD44324182 and µPD44324362 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.
These UPD44324182 are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.
These UPD44324182 are packaged in 165-pin PLASTIC FBGA.