UPC4064

The UPC4064 is a low power J-FET input quad operational amplifier that will operate at voltage levels as low as ±2.0V. The feature of UPC4064 are as follows: (1)low supply current: 800A; (2)very low input bias and offset currents; (3)high input impedance: J-FET input stage; (4)low supply voltage operation; (5)output short circuit protection; (6)internal frequency compensation.

The absolute maximum ratings of the UPC4064 are: (1)voltage between V+ and V-: -0.3 to +36V; (2)differential input voltage: ±30V; (3)input voltage: V-0.3 to V+0.3V; (4)output voltage: V-0.3 to V+0.3V; (5)power dissipation: 570mW; (6)output short circuit duration: indefinite sec; (7)operating temperature range: -20 to +80; (8)storage temperature range: -55 to +125.

The following is about the electrical characteristics of UPC4064: (1)input offset voltage: ±2 mV typical and ±10 mV max at Rs50; (2)input offset current: ±5 pA typical and ±50 pA max; (3)input bias current: 10 pA typical and 100 pA max; (4)large signal voltage gain: 3V/mV min, 9V/mV typical at Rs10k, Vo=±10V; (5)supply current: 800A typical and 1000A max at Io=0A, both amplifiers; (6)common mode rejection ratio: 70dB min, 90dB typical; (7)supply voltage rejection ratio: 70dB min, 90dB typical; (8)unity gain frequency: 1MHz; (9)channel separation: 120dB.