Features: ·Single chip contains both Encoder and Decoder.·3V to 11 V operation.·On chip oscillator uses non-critical RC components.·Cross interference of recetver is virtually eliminated by circuitry which requires 4 valid words to be received, each within 64ms of the other.·Schmitt Trigger input ...
UN13750: Features: ·Single chip contains both Encoder and Decoder.·3V to 11 V operation.·On chip oscillator uses non-critical RC components.·Cross interference of recetver is virtually eliminated by circuitr...
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·Single chip contains both Encoder and Decoder.
·3V to 11 V operation.
·On chip oscillator uses non-critical RC components.
·Cross interference of recetver is virtually eliminated by circuitry which requires 4 valid words to be received, each within 64ms of the other.
·Schmitt Trigger input provides excellent noise immunity.
·Applications. alarm control system, security system cordless telephone, remote control.
·Interfaces with RF, ultrasonic, or infrared modulators I and demodulators
P o w e r S u p p l y V o l t a g e ............ -0 3v to 11v
O p e r a t i n g T e m p e r a t u r e......-20 Deg to 70 D e g C
Storage Temperature (Tstg)..........-55 Deg to 150 Deg C
Applied Voltage on any Pin
........VSSPO.3 < VIN < VDD +o 3
*Comments
Stresses above those ilsted Iunder "Absolute Maximum Ratings" may cause permanent damage to the dewce. These are stress ratings only. Functional operation of this device at these or any other conditions above those indtcated in the operational sections of this specification IS not implled and exposure to absolute maximuln rating c o n d i t i o n s f o r e x t e n d e d pertods may affect device rellability.
The UM3750 Encoder/Decoder is a CMOS/LSI digital code Transmitter-Receiver system. Working in the transmit (encoder) mode, the UM3750 will sequentially encode and transmit 12 bits of input. Each of the 12 bits may be 1 or 0 to allow 4096 different codes. In the receive (decoder) mode, the incoming signal is compared to the local code In a sequential manner Once an error IS detected the system will reset and beain its comparison on the next word. If all 12 bits are received correctly, a "valid" signal is generated. This signal clears a 64ms counter and triggers a 3-stage counter. The 3-stage counter counts the "valid" pluses and when 4 pulses have been detected, the TX/RX output pin goes low. After the TX/RX output pin goes low, the next "valid" must be received within 128ms, giving a one valid in 6 requirement to keep the TX/RX output pin.