UG2265

The UG2 series of ULCs is well suited for conversion of medium- to-large sized CPLDs and FPGAs. Devices are implemented in high-performance CMOS technology with 0.5-m (drawn) channel lengths, and are capable of supporting flip-flop toggle rates of 625 MHz at 5V and 360 MHz at 3.3V, operating clock frequencies up to 150 MHz and input to output delays as fast as 5 ns, 200 ps at 5V.

The architecture of the UG2 series allows for efficient conversion of many PLD architecture and FPGA device types with higher IO count. A compact RAM cell, along with the large number of available gates allows the implementation of RAM in FPGA architectures that support this feature, as well as JTAG boundary-scan and scan-path testing.

Conversion to the UG2 series of ULC can provide a significant reduction in operating power when compared to the original PLD or FPGA. This is especially true when compared to many PLD and CPLD architecture devices, which typically consume 100 mA or more even when not being clocked. The UG2 series has a very low standby consumption of 0.4 nA/gate typically commercial temp, which would yield a standby current of 0.4 nA/gate, 4 mA on a 10,000 gate design. Operating consumption is a strict function of clock frequency, which typically results in a power reduction of 50% to 90% depending on the device being compared.

The UG2 series provides several options for output buffers, including a variety of drive levels up to 24 mA. Schmitt trigger inputs are also an option. A number of techniques are used for improved noise immunity and reduced EMC emissions, including: several independent power supply busses and internal decoupling for isolation; slew rate limited outputs are also available as required.

The UG2 series is designed to allow conversions of high performance 3-V devices as well as 5-V devices. Support of mixed supply conversions is also possible, allowing optimal trade-offs between speed and power consumption.