UCN5810A

The UCN5810A has the following features including 5 MHz Typical Data Input Rate;Low-Power CMOS Logic and Latcfies;60 V or 80 V Source Outputs;Internal Pull-Down Resistors.

Selected devices (suffix-1) have maximum ratings of 80 V and 40 mA per driver. In all other respects,the-basic part and the part with the"-1" suffix are identical.BiMOS II devices have much faster data input rates than the original BiMOS circuits. With a 5 V supply, they will typically operate at better than 5 MHz.With a 12 V supply, significantly higher speeds are obtained.The CMOS inputs cause minimal loading and are compatible with standard CMOS, PMOS, and NMOS circuits.Use of these drivers with TTL or DTL circuits may require appropriate input pull-up resistors to ensure an input logic high. A CMOS serial data output allows cascading for multiple drive-line applications required by many dot matrix, alpha-numeric, and bar graph displays.The UCN5810A is supplied in an 18-pin dual in-line plastic package. under normal operating conditions, this device will allow all outputs to source 25 mA continuously at ambient temperatures up to 60. The UCN5810LW is furnished in a wide-body, small-outline plastic package for minimum-area surface-mount applications.

Serial Data present at the input is transferred to the snltt register on the logic "0" to logic"1" transtion of the CLOCK input pulse.On succeeding CLOCK pulses,the registers shift data intormauon towards the SERIAL DATAOUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE Applications where the latches are bypassed(STROBE tied high) will require that the BLANKING input be high during serial data entry.When the BLANKING input is high, the output source drivers are disabled(OFF);The DMOS sink drivers are ON. The information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled bytheir respective latches.