UA1184

The UA1 series of ULCs is well suited for conversion of large sized CPLDs andFPGAs. Devices are implemented in highperformance CMOS technology with0.35µm (drawn) channel lengths, and are capable of supporting flipflop toggle ratesof 200 MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150psat 3.3V. The architecture of the UA1 series allows for efficient conversion of many PLDarchitecture and FPGA device types with higher IO count. A compact RAM cell, alongwith the large number of available gates allows the implementation of RAM in FPGAarchitectures that support this feature, as well as JTAG boundaryscan and scanpath testing.

Conversion to the UA1 series of ULC can provide a significant reduction in operatingpower when compared to the original PLD or FPGA. This is especially true whencompared to many PLD and CPLD architecture devices, which typically consume100mA or more even when not being clocked. The UA1 series has a very lowstandby consumption of 0.3nA/gate typically commercial temperature, which wouldyield a standby current of 42µA on a 144,000 gates design. Operating consumption isa strict function of clock frequency, which typically results in a power reduction of 50%to 90% depending on the device being compared.

The UA1 series provides several options for output buffers, including a variety of drivelevels up to 18mA. Schmitt trigger inputs are also an option. A number of techniquesare used for improved noise immunity and reduced EMC emissions, including: severalindependent power supply busses and internaldecoupling for isolation; slew rate lim-ited outputs are also available if required. The UA1 series is designed to allowconversion of high performance 3.3V devices as well as 2.5V devices.