U421

Drain Source Voltage VDS :
Drain Current (Idss at Vgs=0) :
Continuous Drain Current :
Gate-Source Breakdown Voltage : - 40 V
Transistor Polarity : P-Channel
Mounting Style : Through Hole
Packaging : Bulk
Configuration : Dual
Package / Case : TO-78


Features:

· Ultra Low Input Bias Current . . . . . . . 250 Fempto Amps
· Low Operating Current
· Tight Matching Characteristics




Application

· Ultra Low Leakage FET Input Op Amps
· Electrometer
· Infrared Detectors
· pH Meters




Specifications

Gate-to-Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±40V
Gate-Drain or Gate-Source Voltage . . . . . . . . . . . .. . . . . . -40V
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Device Dissipation (Each Side), T_A = 25
(Derate 3.2 mW/ oC to 150oC) . . . . . . . . . . . . . . 400mW
Total Device Dissipation, T_A = 25
(Derate 6.0 mW/ to 150) . . . . . . . . . . . . . 750 mW
Storage Temperature Range . . . . . . . . . . . . . -65 to +150

Description

The Calogic U421 Series are Dual N-Channel JFETs on a monolithic structure designed specifically for very high input impedance for differential amplification and impedance matching. This series features ultra low input bias current (250 fempto amps, U421) while offering high gain at low operating currents and tight matching characteristics. These devices are available in chip form for hybrid designs as well as a hermetic TO-78 package.