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TZA3005H

Features: · Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)· Supports reference clock frequencies of 19.44, 38.88,51.84 and 77.76 MHz· Meets Bellcore, ANSI and ITU-T specifications· Meets ITU jitter specification typically to a factor of 2.5· Integral high-frequency PLL for clock...

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SeekIC No. : 004534335 Detail

TZA3005H: Features: · Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)· Supports reference clock frequencies of 19.44, 38.88,51.84 and 77.76 MHz· Meets Bellcore, ANSI and ITU-T specifications...

TZA3005H Data Sheet

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Part Number:
TZA3005H
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)
· Supports reference clock frequencies of 19.44, 38.88,51.84 and 77.76 MHz
· Meets Bellcore, ANSI and ITU-T specifications
· Meets ITU jitter specification typically to a factor of 2.5
· Integral high-frequency PLL for clock generation
· Interface to TTL logic
· Low jitter PECL (Positive Emitter Coupled Logic) interface
· 4 or 8-bit STM1/OC3 TTL data path
· 4 or 8-bit STM4/OC12 TTL data path
· No external filter components required
· QFP64 package
· Diagnostic and line loopback modes
· Lock detect
· LOS (Loss of Signal) input
· Low power (0.9 W typical)
· Selectable frame detection and byte realignment
· Loop timing
· Forward and reverse clocking
· Squelched clock operation
· Self-biased PECL inputs to support AC coupling.


Application

· SDH/SONET modules
· SDH/SONET-based transmission systems
· SDH/SONET test equipment
· ATM (Asynchronous Transfer Mode) over SDH/SONET
· Add drop multiplexers
· Broadband cross-connects
· Section repeaters
· Fibre optic test equipment
· Fibre optic terminators.


Pinout

Connection Diagram


Specifications

SYMBOL
PARAMETER
MIN.
MAX.
UNIT

VCC

 supply voltage -0.5 +6 V
Vn voltage
on any input pin
between two differential PECL input pins
on SDPECL input pin
-0.5
-2
VCC - 3
VCC + 0.5
+ 2
VCC + 0.5
V
V
V
In current
into any TTL output pin
nto any PECL output pin
-8
-50


+8
+1.5


mA
mA

Ptot total power dissipation - 1.5 W
Tstg storage temperature -65 +150 °C
Tj(bias) junction temperature under bias -55 +125 °C
Tcase(bias) case temperature under bias -55 +100 °C



Description

The TZA3005H SDH/SONET transceiver chip is a fully integrated serialization/deserialization STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s)interface device. It performs all necessary serial-to-parallel and parallel-to-serial functions in accordance with SDH/SONET transmission standards. It is suitable for SONET-based applications and can be used in conjunction with the data and clock recovery unit (TZA3004), optical front-end (TZA3023 with TZA3034/44) and a laser driver (TZA3001). A typical network application is shown in Fig.10.

A high-frequency phase-locked loop is used for on-chip clock synthesis, which allows a slower external transmit reference clock to be used. A reference clock of 19.44,38.88, 51.84 or 77.76 MHz can be used to support existing system clocking schemes. The TZA3005H also performs SDH/SONET frame detection.

The low jitter PECL interface ensures that Bellcore, ANSI,and ITU-T bit-error rate requirements are satisfied.The TZA3005H is supplied in a compact QFP64 package.




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