TX19A

The previous section provided an overview of the RISC features which are different from CISC processors. In this section, we explore how the instruction set architecture (ISA) is implemented in the TX19A in comparison to the 870/X and the 900/L1, 8-bit and 16-bit CISC processors from Toshiba.

The TX19A has two ISA modes, 16-bit and 32-bit. The condition that each mode is executed is respectively called as 16 bit ISA mode and 32 bit ISA mode. It provides for efficient run-time switching between 16-bit and 32-bit ISA modes through an instruction. The 16-bit instruction set (MIPS16e+) is not a separate instruction set indeed but a 16-bit extension of the full 32-bit MIPS architecture. The 32-bit ISA has 103 instructions, the 16-bit ISA 128 instructions. Programs will consist of procedures in 16-bit mode for density or in 32-bit mode for performance.

On the other hand, the 870/X and the 900/L1 are both CISC processors having nearly 1000 types of instructions and many addressing modes. CISC processors are, in general, excel in code efficiency.