TWSI

BASIC INTERFACE OPERATION
All I/O to and from the TWSI core is synchronous to the system clock, CLK.

Before any operation of the MC-TWSI core, the ENABLE must first be asserted. This must be done via a register on the host interface.

For a TWSI master to initiate a transaction on the bus, the host sets up the ADDR_IN, DATA_IN and TWSI_CMD ports and strobes the START input for one clock and performs other operations until either REQ_DATA (in the case of a write) or DATA_VLD (in the case of a read) is asserted. Also, the SLAVE_TIMEOUT (STATUS[0]) and BUSLOSS (STATUS[1]) bits should be polled in case the slave does not respond or the master loses arbitration. The BUSLOSS status bit will be asserted if the interface lost the bus to another master before comp letion of the cycle. The SLAVE_TIMEOUT bit will be asserted if the slave does not respond with a NACK when required. For either of these error conditions, the host must retry the current cycle by strobing START. Note that for burst operations the host is responsible for writing the incremented address into the ADDRESS Register before retrying the operation.

The diagram on the first page shows the Block Diagram of the MC-ACT-16550 Core. The  MC-ACT-16550  core is partitioned into  odules. These modules are described below.