Features: ` Analog Channels -6 dB to 6 dB Analog Gain Analog Input MUXs Auto Video Clamp Three Digitizing Channels, Each WithIndependently Controllable Clamp, PGA,and ADC Clamping: Selectable Clamping Between Bottom Level and Mid-level Offset: 1024-Step Programmable RGB or YPbPr Offset Control PGA...
TVP7000: Features: ` Analog Channels -6 dB to 6 dB Analog Gain Analog Input MUXs Auto Video Clamp Three Digitizing Channels, Each WithIndependently Controllable Clamp, PGA,and ADC Clamping: Selectable Clampi...
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Video A/D Converter ICs Triple 8/10B 150/110 MSPS Video ADC
UNIT | ||
Supply voltage range | IOVDD to IOGND |
0.5 V to 4.5 V |
DVDD to GND |
0.5 V to 2.3 V | |
PLL_A18VDD to PLL_A18GND and A18VDD to A18GND |
0.5 V to 2.3 V | |
A33VDD to A33GND |
0.5 V to 4.5 V | |
Digital input voltage range | VI to GND |
0.5 V to 4.5 V |
Analog input voltage range | AI to A33GND |
0.2 V to 2.3 V |
Digital output voltage range | VO to GND |
0.5 V to 4.5 V |
TA Operating free-air temperature |
0°C to 70°C | |
Tstg Storage temperature |
65°C to 150°C |
TVP7000 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces.The device supports pixel rates up to 150 MHz.Therefore, it can be used for PC graphics digitizing up to the VESA standard of SXGA (1280 ´ 1024) resolution at 75 Hz screen refresh rate, and in video environments for the digitizing of digital TV formats,including HDTV up to 1080p. TVP7000 can be used to digitize CVBS and S-Video signal with 10-bit ADCs.
The TVP7000 is powered from 3.3-V and 1.8-V supply and integrates a triple high-performance A/D converter with clamping functions and variable gain,independently programmable for each channel. The clamping timing window is provided by an external pulse or can be generated internally. It includes analog slicing circuitry on the Y or G input to support sync-on-luminance or sync-on-green extraction. In addition, TVP7000 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.
TVP7000 also contains a complete analog PLL block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 150
MHz.
All programming of the part is done via an indus-try-standard I2C interface, which supports both reading and writing of register settings. The TVP7000 is available in a space-saving TQFP 100-pin PowerPAD package.