TUSB6020

` USB On-the-Go (OTG) Controller Core Use 19.200-MHz, 24.000-MHz, or
Use Mentor Graphics USB 2.0 OTG Core 48.000-MHz Reference Clock Input as a
Dual-Role Controller Can Operate Either as Crystal or External Clock Driver a Function Controller for a USB Peripheral At-Speed Built-In Self Test (BIST) With or as the Host/Peripheral in Point-to-Point Internal Asynchronous Capability Through or Multi-Point Communications With Other Loopback USB Functions
On-Chip Integrated Accurate 45-W
Compliant With the USB 2.0 Standard for High-Speed Termination, 1.5-kW Pullup, High-Speed (480-Mbps) Functions and and 15-kW Pulldown Resistors With the OTG Supplement to the USB 2.0
On-Chip Phase-Locked Loop (PLL) to Specification Reduce Noise on the High-Speed Clocks
Supports OTG Communications With One
Active Power Consumption Less Than or More High-, Full-, or Low-Speed Devices 100 mW
Supports Session Request Protocol (SRP)
` VLYNQ 2.0 Interface to External Host and Host Negotiation Protocol (HNP) Controller
Supports Suspend-and-Resume Signaling
High-Speed (150-MHz) Point-to-Point Serial
Configurable for up to 15 Transmit Interface for Direct Connection to Other Endpoints and up to 15 Receive Endpoints VLYNQ Interface
Configurable FIFOs, Including the Option
Supports 4X RX and 4X TX Lines of Dynamic FIFO Sizing
Memory-Mapped Master/Slave
16k-Byte RAM for USB Endpoint FIFO
Hardware Flow Control Internal Loopback Shared by USB In/Out Endpoints Mode
Support for External Direct Memory
Multichannel DMA Controller Access (DMA) to FIFOs
Integrated List Processor Capable of
Soft Connect/Disconnect Option Parsing Communications Port
Performs All Transaction Scheduling in Programming Interface (CPPI) Hardware 3.0-Compliant Buffer Descriptors
` Integrated USB 2.0 OTG PHY
` System Control Module
Fully Compliant With USB 2.0 Standard
Controls Clock and Reset Generation andand USB 2.0 Transceiver  Macrocell Distribution Interface (UTMI) Revision 1.05
Controls and Observes Device Power
Optimized One-Port Operation at Low States Speed (1.5 Mbps), Full Speed (12 Mbps),
Controls Test and Debug Modes and High Speed (480 Mbps)
Supports External Power Management
Support for External Charge Pump
` VBUS Switched Central Resource
Supports UTMI+3 Level 3 (Host and OTG
Supports Two VBUSP Master and Three Devices, High/Full/Low Speed and VBUSP Slave Interfaces Preamble Packet)
` High-Performance 80-Pin
Protection Circuitry to Withstand Possible MicroStar BGA™/MicroStar Junior™ VBUS Short ZQE Package

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

The TUSB6020 is a USB 2.0 high-speed, on-the-go (OTG) dual-role controller designed for a seamless interface
to the VLYNQ serial interface, and is ideal for a wide range of applications. The USB OTG dual-role controller can operate either as a function controller for a USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other functions. The integrated USB 2.0 PHY provides one-port operation at low speed (1.5 Mbps), full speed (12 Mbps), and high speed (480 Mbps). TUSB6020 is configured as an interrupt or wake-up source, and some GPIOs have secondary functions dedicated to the USB 2.0 operation. The VLYNQ serial interface is a low pin count, high-speed, point-to-point interface.

The TUSB6020 device is fully compliant with Universal Serial Bus Specification Revision 2.0 and On-The-Go Supplement to
the USB Specification Revision 1.2.The device operates from 40°C to 85°C free air temperature.