Features: ` TTRN012G5 supports OC-48/STM-16 data rate` TTRN012G7 supports:- OC-48/STM-16 data rate- RS (255, 239) forward error correction (FEC) OC-48/STM-16 data rate` Fully integrated clock synthesizer and 16:1 data multiplexer` Supports clockless data transfer into the 16:1 multiplexer` Parity ...
TTRN012G5: Features: ` TTRN012G5 supports OC-48/STM-16 data rate` TTRN012G7 supports:- OC-48/STM-16 data rate- RS (255, 239) forward error correction (FEC) OC-48/STM-16 data rate` Fully integrated clock synthe...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Parameter |
Min |
Max |
Unit |
Power Supply Voltage (VCC) |
- |
4.0 |
V |
Storage Temperature |
40 |
125 |
|
Pin Voltage |
GND0.5 |
VCC + 0.5 |
V |
The Lucent Technologies Microelectronics Group TTRN012G5 operates at the OC-48/STM-16 data rate of 2.5 Gbits/s. The TTRN012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of 2.7 Gbits/s. For clarity, this data sheet refers to the TTRN012G5 serial data rate as 2.5 Gbits/s and the parallel data and reference clock frequency as 155 MHz. (The precise rates are 2.48832 Gbits/s and 155.52 MHz.) When using the TTRN012G7 at the FEC rate, the 2.5 Gbits/s data rate should be interpreted as 2.7 Gbits/s and the parallel and clock frequency should be interpreted as 166 MHz. (The precise rates are 2.66606 Gbits/s and 166.62 MHz.)
The devices provide a 16:1 multiplexer and clock multiplier unit. Both a high-speed serial clock and data output are generated. The devices accept 16 differential PECL data inputs and a low-speed reference clock. A unique feature of the multiplexer is that no clock is required to feed in the 16 data lines, as long as the upstream data chip clock is synchronous with the device REFCLKP/N input.
Alternatively, contra-clocking may be used, whereby the device provides one of four phases of a 155.52 MHz or 166.62 MHz clock output back upstream to the data chip.
Other features include a parity bit input and parity check on the 16 input data lines, a second 2.5 Gbits/s or 2.7 Gbits/s data output for loopback toward the TRCV012G5 or TRCV012G7 device, and a user-configurable PLL bandwidth. Both devices are available in either BiCMOS or in SiGe BiCMOS technology for lower power operation.