TSRD1003G

The TSRD1003G is designed as a high-speed serializer/deserializer (SERDES) macrocell. This macro cell includes a current mode logic (CML) high-speed serial interface and makes use of a proprietary CDR architecture along with the sharing of a PLL across multiple RX and TX channels to reduce area and power consumption.These characteristics make it suitable for applications that require high channel counts.

It has some features,they are:designed to operate in Ethernet, fibre channel,InfiniBand™, and SONET/SDH (synchronous digital hierarchy)applications ; selectable data rate(1.06 Gbits/s-3.2 Gbits/s);100 MHz-168 MHz reference clock frequency range;16-bit or 20-bit parallel I/O interface in full-rate mode ; programmable control and configuration interface to define the various device configurations ;analog modularity and digital library interface for design flexibility;automatic lock-to-reference in absence of receive data;CML high-speed interface I/O for use with backplane or cable media;programmable transmit pre-emphasis optimized for backplane applications;requires one external resistor for bias current generation;requires no external components for clock recovery and frequency synthesis;105 mW per transceiver (typical);low powerdown dissipation;half amplitude mode for reduced power consumption in chip-to-chip applications;1.5 V±5% power supply;1.8 V±5% power supply option for differential high-speed I/O circuits;0°C-125°C junction temperature.

The TSRD1003G can be used in SONET,fibre channel,inifiniband and 10 gbit ethernet (XAUI).If you want to know more information about it,please download the datasheet on www.chinaicmart.com and www.seekic.com