TSM67V05

Features:

3.3 V ± 0.3 V low voltage only
Fast access time 35 ns to 70 ns
Wide temperature range : 55 ° to +125 °C
TSM67V05 L low power TSM67V05 V very low power
Expandable data bus to 16 bits or more using master/slave chip select when using more than one device on chip arbitration logic
Versatile pin select for master or slave :
  M/S = H for busy output flag on master
  M/S = L for busy input flag on slave
INT flag for port to port communication
Full hardware support of semaphore signaling between ports
Fully asynchronous operation from either port
Battery back up operation : 2 V data retention


Pinout




Specifications

Supply voltage (VCC GND) . . . . . . . . . . . . . . . . . . 0.3 V to 7.0 V
Input or Output voltage applied : . . . . . . . . . . . . . . (GND 0.3 V) to (Vcc + 0.3 V)
Storage temperature : . . . . . . . . . . . . . . . . . . . . . . 65 to + 150
* Notice
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extented periods may affect reliability.

OPERATING RANGE	OPERATING SUPPLY VOLTAGE	OPERATING TEMPERATURE
Military	Vcc = 3.3 V ± 0.3 %	55 to + 125
Automotive	Vcc = 3.3 V ± 0.3 %	40 to + 125
Industrial	Vcc = 3.3 V ± 0.3 %	40 to + 85
Commercial	Vcc = 3.3 V ± 0.3 %	0 to + 70

Description

The TSM67V05 is a very low power CMOS dual port static RAM organized as 8192 * 8. The TSM67V 05 is designed to be used as a stand-alone 8 bit dual port RAM or as a combination MASTER/SLAVE dual port for 16 bit or more width systems. Using the TEMIC MASTER/SLAVE dual port approach in memory system applications results in full speed, error free operation without the need for additional discrete logic.

TSM67V05 Master and slave devices provide two independant ports with separate control, address and I/O pins that permit independant, asynchronous access for reads and writes to any location in the memory. An automatic power down feature controlled by CS permits the onchip circuitry of each port in order to enter a very low stand-by power mode.

Using an array of eight transistors (8T) memory cell and fabricated with the state of the art 0.65 mm lithography named SCMOS, the TSM67V05 combines an extremely low standby supply current (typ = 1.0 A) with a fast access time at 35 ns over the full temperature range. All versions offer battery backup data retention capability with a typical power consumption at less than 3.3 W.

For military/space applications that demand superior levels of performance and reliability the TSM67V05 is processed according to the methods of the latest revision of the MIL STD 883 (class B or S) and/or ESA SCC 9000.