Operating Supply Voltage
:
Supply Current
:
Mounting Style
:
Package / Case
:
Maximum Operating Temperature
: + 70 C
Minimum Operating Temperature
: 0 C
Peak Wavelength
: 640 nm
Packaging
: Tray
Features: 1536 * 1 Sensor-Element Organization
400 Dot-Per-Inch (DPI) Sensor Pitch
High Linearity and Uniformity
Wide Dynamic Range . . . 4000:1 (72 dB)
Output Referenced to Ground
Low Image Lag . . . 0.5% Typ
Operation to 8 MHz
Single 3-V to 5-V Supply
Rail-to-Rail Output Swing (AO)
No External Load Resistor RequiredSpecificationsSupply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V
Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . −20 mA to 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Voltage range applied to any output in the high impedance or power-off state, VO . . . −0.3 V to VDD + 0.3 V
Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . −25 mA to 25 mA
Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . −40 mA to 40 mA
Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA
Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . −25 to 85
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 to 85
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
† Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.DescriptionThe TSL1412S linear sensor array consists of 2 sections of 768 photodiodes, each with associated charge amplifier circuitry, aligned to form a contiguous 1536 * 1 pixel array. The device incorporates a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 m by 55.5 m with 63.5-m center-to-center spacing and 8-m spacing between pixels. Operation is simplified by internal logic that requires only a serial-input (SI) pulse and a clock.
The TSL1412S is intended for use in a wide variety of applications including mark and code reading, OCR and contact imaging, edge detection and positioning, and optical encoding.
The TSL1412S consists of 1536 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time.
The output and reset of the TSL1412S are controlled by a 768-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1 are connected together. This causes all 768 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO.
The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins.
On the 768th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (when SO1 is connected to SI2). The rising edge of the 769th clock cycle terminates the SO1 pulse, and returns the analog output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 1536th clock pulse. Note that a 1537th clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of tqt (pixel charge transfer time) after the 1537th clock pulse. Sections may be operated in parallel or in serial fashion.
AO is an op amp-type output that does not require an external pull-down resistor. The design of TSL1412S allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the TSL1412S is not in the output phase, AO is in a high-impedance state.
TSL1412S Data Sheet
