TSC21020F

· Superscalar IEEE Floating-Point-Processor
· Off-Chip Harvard Architecture Maximizes Signal Processing Performance
· 50 ns, 20 MIPS Instruction Rate, Single-Cycle Execution
· 60 MFLOPS Peak, 40 MFLOPS Sustained Performance
· 1024-Point Complex FFT Benchmark : 0.975 ms
· Divide (y/x) : 300 ns
· Inverse Square Root (1//x) : 450 ns
· 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats
· 32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators
· IEEE Exception Handling with Interrupt on Exception
· Three Independent Computation Units : Multiplier, ALU, and Barrel Shifter
· Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes
· Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations
· Multiply with Add & Subtract for FFT Butterfly Computation
· Efficient Program Sequencing with Zero-Overhead Looping : Single-Cycle Loop Setup
· Single-Cycle Register File Context Switch
· 23 ns External RAM Access Time for Zero-Wait-State, 40 ns Instruction Execution
· IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry
· 223 CPGA package for breadboarding
· 256 Multi layer quad flat pack, flat leads, for flight models
· Full compatible with Analog Devices ADSP-21020
· Latch up immune
· Total dose better than 100 Krad (Si)
· SEU immunity better than 50 MeV/mg/cm²
· For 25 MHz specification, call factory

Supply Voltage . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . -0.5 V to + 7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . .. . . -0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Operating Temperature Range (Ambient) . .  . . . . -55°C to + 125°C
Storage Temperature Range . . . . . . . . . . . . . . . . -65°C to + 150°C
* Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

The TSC21020F is single-chip IEEE floating-point processor optimized for digital signal processing applications1. Its architecture is similar to that of Analog Devices' ADSP-2100 family of fixed-point DSP processors.

Fabricated in a high-speed, low-power and radiation tolerant CMOS process, the TSC21020F has a 50 ns instruction cycle time. With a high-performance on-chip instruction cache, the TSC21020F can execute every instruction in a single cycle.

The TSC21020F features :
` Independent Parallel Computation Units The arithmetic/logic unit (ALU), multiplier and shifter perform single-cycle instructions. The units are architecturally arranged in parallel, maximizing computational throughput. A single multifunction instruction executes parallel ALU and multiplier operations. These computation units support IEEE 32-bit single-precision floating-point, extended precision 40-bit floating-point, and 32-bit fixed-point data formats.

` Data Register File
A general-purpose data register file is used for transferring data between the computation units and the data buses, and for storing intermediate results. This 10-port (16-register) register file, combined with the TSC21020F's Harvard architecture, allows unconstrained data flow between computation units and off-chip memory.

` Single-Cycle Fetch of Instruction and Two Operands
The TSC21020F uses a modified Harvard architecture in which data memory stores data and program memory stores both instructions and data. Because of its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch an operand from data memory, an operand from program memory, and an instruction from the cache, all in a single cycle.

` Memory Interface
Addressing of external memory devices by the TSC21020F is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. Separate control lines are also generated for simplified addressing of page-mode DRAM. The TSC21020F provides programmable memory wait states, and external memory acknowledge controls allow interfacing to peripheral devices with variable access times.

` Instruction Cache
The TSC21020F includes a high performance instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective-only the instructions whose fetches conflict with program memory data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates and FFT butterfly processing.

` Hardware Circular Buffers
The TSC21020F provides hardware to implement circular buffers in memory, which are common in digital filters and Fourier transform implementations. It handles address pointer wraparound, reducing overhead (thereby increasing performance) and simplifying implementation. Circular buffers can start and end at any location.

` Flexible Instruction Set
The TSC21020F's 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the TSC21020F can conditionally execute a multiply, an add, a subtract and a branch in a single instruction.