TSB21LV03A

The TSB21LV03A provides the analog and digital physical layer functions needed to implement a three-port node in a cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB21LV03A is designed to interface with a link-layer controller (LLC), such as the TSB12LV21A, TSB12LV31, or TSB12C01A.

The TSB21LV03A requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The 196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. For the TSB21LV03A, the 49.152 MHz clock output is active when RESET is asserted low. The power-down function, when enabled by taking the PD terminal high, stops operation of the PLL and disables all circuitry except the cable-not-active signal circuitry.

The TSB21LV03A supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the link interface outputs behave normally. Also, whenISO is tied high, the internal bus hold function is enabled for use with the TI Bus Holder (patent pending) isolation. TI bus holder isolation is implemented when ISO is tied
high.