TS825 Series

      The TS825 Series is Microprocessor Supervisory Circuit with Watchdog Timer & Manual Reset designed for Computers and Controllers;Embedded Controllers;Intelligent instruments;Critical uP monitoring;Portable / Battery powered equipment;Automotive Systems.The TS825 Series has the following features including Precision monitoring of +3V, +3.3V and +5V power supply voltage;Tight voltage threshold tolerance +/-1.5%;Fully specified over temperature;210mS min. power-on reset pulse width;3uA(typ) supply current;Guaranteed reset valid to Vdd = +1V;Power supply transient immunity;No external components.
      The TS825 family allows the user to customize the CPU monitoring function without any external components. The user has a large choice of reset voltage thresholds and output driver configurations, all of which are present ant the factory. Each wafer is trimmed to the customer's specifications.These circuits will ignore fast negative going transients on Vdd. The state of the reset output is guaranteed to be correct down to 1V. After Vdd crosses above a factory present threshold, the TS823/824/825 assert a reset signal.After a predetermined time (the "reset" interval) the reset is deasserted. If Vdd ever drops below the threshold voltage a reset is asserted immediately. In addition to a supply monitoring function the TS823/824/825 also monitor transitions at the watchdog (WDI) input. If a logic transition does not occur at the WDI pin within a certain time interval (the"watchdog" interval) then a reset is asserted. The reset deasserts after the reset interval, as explained earlier.The TS823/824/825 can both assert a reset manually by pulling the MR input to ground, and the micro-power quiescent current make this family a natural for portable battery powered equipment.
      The TS825are designed to interface with the reset input of a microprocessor and to prevent CPU execution errors due to power up, power down, and other power supply errors. The TS823/824 also monitor the CPU health by checking for signal transitions form the CPU at the WDI input.