TS80C51U2

Features:

80C52 Compatible
  ` 8051 pin and instruction compatible
  ` Four 8-bit I/O ports
  ` Three 16-bit timer/counters
  ` 256 bytes scratchpad RAM
High-Speed Architecture
  ` 40 MHz @ 5V, 30MHz @ 3V
  ` X2 Speed Improvement capability (6 clocks/ machine cycle) 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V)
second UART
Baud Rate Generator
Dual Data Pointer
On-chip ROM/EPROM (16K-bytes)
Programmable Clock Out and Up/Down Timer/ Counter 2
Hardware Watchdog Timer (One-time enabled with Reset-Out)
Asynchronous port reset
Interrupt Structure with
  ` 7 Interrupt sources
  ` 4 level priority interrupt system
Full duplex Enhanced UARTs
  ` Framing error detection
  ` Automatic address recognition
Low EMI (inhibit ALE)
Power Control modes
  ` Idle mode
  ` Power-down mode
  ` Power-off Flag
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44 (window), CDIL40 (window)


Pinout




Specifications

Ambiant Temperature Under Bias:
C = commercial                                         0°C to 70°C
I = industrial                                            -40°C to 85°C
Storage Temperature                              -65°C to + 150°C
Voltage on V_CC to V_SS                             -0.5 V to + 7 V
Voltage on V_PP to V_SS                             -0.5 V to + 13 V
Voltage on Any Pin to V_SS                       -0.5 V to V_CC + 0.5 V
Power Dissipation                                  1 W⁽²⁾

NOTES
1. Stresses at or above those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.


Description

TEMIC TS80C51U2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller.

The TS80C51U2 retains all features of the TEMIC 80C51 with extended ROM/EPROM capacity (16 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/ counters.

In addition, the TS80C51U2 has a second UART, enhanced functions on both UART, enhanced timer 2, a hardware watchdog timer, a dual data pointer, a baud rate generator and a X2 speed improvement mechanism.

The fully static design of the TS80C51U2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data.

The TS80C51U2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative.