TS5N118

Features:

` Low and Flat ON-State Resistance (r<sub>on</sub>) Characteristics Over Operating Range  (r<sub>on</sub> = 3 W Typ)
` 0- to 10-V Switching on Data I/O Ports
` Bidirectional Data Flow With Near-Zero Propagation Delay
` Low Input/Output Capacitance Minimizes Loading and Signal Distortion (C_io(OFF) = 20 pF Max, B Port)
` V<sub>CC</sub> Operating Range From 4.75 V to 5.25 V
` Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
` ESD Performance Tested Per JESD 22
2000-V Human-Body Model (A114-B, Class II)
1000-V Charged-Device Model (C101)
` Supports Both Digital and Analog Applications


Application

· PCI Interface
· Differential Signal Interface
· Memory Interleaving
· Bus Isolation
· Low-Distortion Signal Gating


Pinout




Specifications

		MIN	MAX	UNIT
VCC Supply voltage range		0.5	7	V
VIN Control input voltage range(2) (3)		0.5	7	V
VI/O Switch I/O voltage range(2) (3) (4)		0.5	11	V
II/O ON-state switch current(5)			±100	mA
Continuous current through VCC or GND			±100	mA
JA Package thermal impedance(6)	DBQ package		90	/W
	PW package		108
Tstg Storage temperature range		65	150

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.  hese are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device  eliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) V_I and V_O are used to denote specific conditions for V_I/O.
(5) I_I and I_O are used to denote specific conditions for I_I/O.
(6) The package thermal impedance is calculated in accordance with JESD 51-7.


Description

The TS5N118 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass
transistor, providing a low and flat ON-state resistance (r_on). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the TS5N118 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The TS5N118 is a 1-of-8 multiplexer/demultiplexer with a single output-enable (OE input. The select (S0, S1, S2) inputs control the data path of the multiplexer/demultiplexer. When OE is low, the multiplexer/demultiplexer is enabled and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the multiplexer/demultiplexer is disabled and a high-impedance state exists between the A and B ports.

This TS5N118 is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through