Features: ` Offers Bandwidth Allocation of PCI Express™ Signal Using Two-Lane 1:2Multiplexer/Demultiplexer` Vcc Operating Range From 1.7 V to 1.9 V` Supports Data Rates of 2.5 Gbps` Port-Port Crosstalk (39 dB at 1.25 GHz)` OFF Port Isolation (38 dB at 1.25 GHz)` Low ON-State Resistance (10 W...
TS2PCIE2212: Features: ` Offers Bandwidth Allocation of PCI Express™ Signal Using Two-Lane 1:2Multiplexer/Demultiplexer` Vcc Operating Range From 1.7 V to 1.9 V` Supports Data Rates of 2.5 Gbps` Port-Port ...
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Multiplexer Switch ICs 2Ch PCIe 2:1 Mux/ Demux Passive FET Sw
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Multiplexer Switch ICs 4CH PCIe 8:16 Mux/ Demux Passive FET Sw
` Offers Bandwidth Allocation of PCI Express™
Signal Using Two-Lane 1:2
Multiplexer/Demultiplexer
` Vcc Operating Range From 1.7 V to 1.9 V
` Supports Data Rates of 2.5 Gbps
` Port-Port Crosstalk (39 dB at 1.25 GHz)
` OFF Port Isolation (38 dB at 1.25 GHz)
` Low ON-State Resistance (10 W Typ)
` Low Input/Output Capacitance (3.5 pF Typ)
` Excellent Differential Skew (5 ps Max)
` Minimal Propagation Delay
` ESD Performance Tested Per JESD 22
2000-V Human-Body Model (A114-B, Class II)
1000-V Charged-Device Model (C101)
MIN MAX | UNIT | ||
VDD Supply voltage range | 0.5 2.5 | V | |
VIN Control input voltage range(2) (3) | 0.5 2.5 | V | |
VI/O Switch I/O voltage range(2) (3) (4) | 0.5 2.5 | V | |
IIK Control input clamp current | VIN < 0 and VI/O < 0 | 50 | mA |
II/OK I/O port clamp current | VIN < 0 and VI/O < 0 | 50 | mA |
II/O ON-state switch current(5) | ±100 | mA | |
Continuous current through VDD or GND | ±100 | mA | |
JA Package thermal impedance(6) | TBD | /W | |
Tstg Storage temperature range | 65 150 |
The TS2PCIE2212 can be used to muxltiplex/demultiplex two PCI Express™ lanes, each representing differential pairs of receive (RX) and transmit (TX) signals. The switch TS2PCIE2212 operates at the PCI Express bandwidth standard of 2.5-Gbps signal-processing speed. The device is composed of two banks, with each bank accommodating two sources (source A and source B) and two destinations (destination A and destination B).
When a logic-level low of TS2PCIE2212 is applied to the control (CTRL) pin, source A is connected to destination A and source B is connected to destination B. When a logic-level high is applied to CTRL, source A is connected to destination B, while source B and destination A are open.