Features: • Single-chip 1:32 Demultiplexer with integrated clock and data recovery• Differential Analog Data Input• SONET/SDH compliant for 2.48832 Gb/s jitter tolerance & transfer• Internal PLL with NRZ phase detector ensures sampling of incoming data stream occurs in ...
TQ8223: Features: • Single-chip 1:32 Demultiplexer with integrated clock and data recovery• Differential Analog Data Input• SONET/SDH compliant for 2.48832 Gb/s jitter tolerance & tran...
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Parameter | Symbol | Min | Max | Unit |
Supply voltage | VDD-VEE | GND | 7.0 | V |
Internal VCO Supply voltage | VOSC | VEE-0.5 | VDD+0.5 | V |
DIN,NDIN termination voltage | VTD | VEE-0.5 | VDD+0.5 | V |
Inputs/Outputs | VEE-0.5 | VDD+0.5 | V | |
Storage Temperature | Tstg | -55 | 150 | |
Maximum Case Operating Temperature, | Tc | 125 | ||
Maximum junction temperature | Tj | 120 | ||
Electrostatic Discharge (100 pF, 1.5 kW) | 1000 | V |
The TQ8223 is a multi-configuration SONET/SDH OC48/STM16 CDR/ DEMUX that regenerates and re-times serial 2.48832 Gb/s data. It recovers the 2.48832 GHz clock from the data stream and frequency divides it to generate control signals and clocks used to perform the demultiplexing function.
The TQ8223 is extremely flexible for telecom, ATM and networking applications. The serial 2.48832 Gb/s data stream is demultiplexed into a 32-bit wide 77.76 MHz TTL data bus. Internal data inversion is also available. The device generates byte-wise parity check bits for the demultiplexed data and provides associated clock outputs for the different modes. Parity checking is not required for normal device operation. The TQ8223 provides added flexibility through a selectable internal/external Voltage Controlled Oscillator(VCO) as well as a selectable internal Phase Locked Loop (PLL). If an external high frequency clock is utilized a singleended or differential AC coupled clock may be used.
The internal PLL TQ8223 contains a NRZ phase detector which enables it to adjust the phase of the internal clock such that sampling of the incoming data stream occurs in the middle of the the data eye. An offset control allows adjustment ±125 pS around this nominal position. Operating from a single +5V supply, the TQ8223 provides fully compliant functionality and performance.
The TQ8223 is fully compliant with SONET/SDH jitter tolerance and transfer specifications. A TTL level LOCK signal is supplied to indicate when the frequency difference between the internal 38.88 MHz clock and the external 38.88 MHz clock is less than 488 ppm.