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TQ2061

Features: • One differential PECL output: 600 mV (min) swing• Common-mode voltage: VDD 1.2 V (max) VDD 1.6 V (min)• Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max)• Reference clock input: 25 MHz to 35 MHz TTL-level crystal oscillator•...

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SeekIC No. : 004527803 Detail

TQ2061: Features: • One differential PECL output: 600 mV (min) swing• Common-mode voltage: VDD 1.2 V (max) VDD 1.6 V (min)• Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps p...

TQ2061 Data Sheet

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Part Number:
TQ2061
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• One differential PECL output: 600 mV (min) swing
• Common-mode voltage:
   VDD 1.2 V (max)
   VDD 1.6 V (min)
• Period-to-period output jitter:
   25 ps peak-to-peak (typ)
   70 ps peak-to-peak (max)
• Reference clock input: 25 MHz to 35 MHz TTL-level crystal oscillator
• Self-contained loop filter
• Optional 200 W pull-down resistors for AC-coupled outputs
• +5 V power supply
• 28-pin J-lead surface-mount package
• Ideal for designs based on DEC Alpha AXP™ processors


Pinout

Connection Diagram


Specifications

Storage temperature                                                   
65 °C to +150 °C
Ambient temperature with power applied               
55 °C to +110 °C
Supply voltage to ground potential                              
0.5 V to +7.0 V
DC input voltage                                                          
0.5 V to +(VDD + 0.5)V
DC input current                                                         
30 mA to +5 mA
Package thermal resistance (MQuad)                          
JA = 45 °C/W
Die junction temperature                                            
TJ = 150 ° C



Description

TriQuint's TQ2061 is a high-frequency clock generator. It utilizes a 25 MHz to 35 MHz TTL input to generate a 500 MHz to 700 MHz PECL output. The TQ2061 has a completely self-contained Phase-Locked Loop (PLL) running at 500 MHz to 700 MHz. This stable PLL allows for a low period-to-period output jitter of 70 ps (max), and enables tight duty cycle control of 55% to 45% (worst case).

The TQ2061 provides optional 200-ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN), and pin 23 (PDR1) should be connected to pin 22 (Q).

Various test modes on the TQ2061 simplify debug and testing of systems by slowing the clock output or by bypassing the PLL.




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