TPS75401-EP

Features:

 Controlled Baseline
One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree†
2-A Low-Dropout Voltage Regulator
Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V Fixed Output and Adjustable Versions
Open Drain Power-On Reset With 100-ms Delay (TPS752xx)
Open Drain Power-Good (PG) Status Output (TPS754xx)
Dropout Voltage Typically 210 mV at 2 A (TPS75233)
Ultralow 75-µA Typical Quiescent Current
Fast Transient Response
2% Tolerance Over Specified Conditions for Fixed-Output Versions
20-Pin TSSOP (PWP) PowerPAD^TM Package
Thermal Shutdown Protection



Pinout




Specifications

Input voltage range‡, V_I  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to 5.5 V
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...0.3 V to 16.5 V
Maximum RESET voltage (TPS752xx)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Maximum PG voltage (TPS754xx)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Peak output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  Internally limited
Output voltage, V_O (OUTPUT, FB)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . ..See dissipation rating tables
Operating virtual junction temperature range, T_J . . . . . . . . . . . . . . . . . . . . . .       .40°C to 125°C
Storage temperature range, T_stg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 kV


Description

   The TPS75401-EP are low dropout regulators with integrated power-on reset and power good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233, TPS75433). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. TPS75401-EP are designed to have fast transient response for larger load current changes.

   Because the PMOS device TPS75401-EP behaves as a low-value resistor, the dropout voltage is very low (typically 210 mV at an output current of 2 A for the TPS75x33) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These TPS75401-EP two key specifications yield a significant improvement in operating life for battery-powered systems.

   The TPS75401-EP is enabled when the EN pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 1 µA at T_J = 25°C.

   The RESET (SVS, POR, or power on reset) output of the TPS75401-EP initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS75401-EP monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage.