Features: ` Available in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V Fixed-Output and Adjustable Versions
` Integrated Precision Supply-Voltage Supervisor Monitoring Regulator Output Voltage
` Active-Low Reset Signal with 200-ms Pulse Width
` Very Low Dropout Voltage . . . Maximum of 35 mV at IO = 100 mA (TPS7350)
` Low Quiescent Current Independent of Load . . . 340 A Typ
` Extremely Low Sleep-State Current, 0.5 A Max
` 2% Tolerance Over Full Range of Load, Line, and Temperature for Fixed-Output Versions§
` Output Current Range of 0 mA to 500 mA
` TSSOP Package Option Offers Reduced Component Height For Critical ApplicationsPinout
SpecificationsInput voltage range§, VI, RESET, SENSE,EN . . . . . . . . . . . . . . . 0.3 V to 11 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Continuous total power dissipation . . . . See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . 55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . .65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . 260°C
‡ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
§ All voltage values are with respect to network terminal ground.
DescriptionThe TPS7333Q devices are members of a family of micropower low-dropout (LDO) voltage regulators. They are differentiated from the TPS71xx and TPS72xx LDOs by their integrated delayed microprocessor-reset function. If the precision delayed reset is not required, the TPS71xx and TPS72xx should be considered.¶
The RESET output of the TPS7333Q initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.
If that occurs, the RESET output of TPS7333Q (open-drain NMOS) turns on, taking the RESET signal low. RESET stays low for the duration of the undervoltage condition. Once the undervoltage condition ceases, a 200-ms (typ) time-out begins. At the completion of the 200-ms delay, RESET goes high.
An order of magnitude reduction in dropout voltage and quiescent current over conventional LDO performance of TPS7333Q is achieved by replacing the typical pnp pass transistor with a PMOS device.
Because the PMOS device TPS7333Q behaves as a low-value resistor, the dropout voltage is very low (maximum of 35 mV at an output current of 100 mA for the TPS7350) and is directly proportional to the output current (see Figure 1). Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current of TPS7333Q is low and remains constant, independent of output loading (typically 340 A over the full range of output current, 0 mA to 500 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The LDO family TPS7333Q also features a sleep mode; applying a logic high signal to EN (enable) shuts down the regulator, reducing the quiescent current to 0.5 A maximum at TJ = 25°C.
The TPS7333Q is offered in 2.5-V, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for the 2.5 V and the adjustable version). The TPS7333Q family is available in PDIP (8 pin), SO (8 pin) and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2 mm.
TPS7333Q Data Sheet
