Features: ` Dual Output Voltages for Split-Supply Applications
` Selectable Power Up Sequencing for DSP Applications
` Output Current Range of 250 mA on Regulator 1 and 125 mA on Regulator 2
` Fast Transient Response
` Voltage Options are 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable Outputs
` Open Drain Power-On Reset With 120-ms Delay
` Open Drain Power Good for Regulator 1
` Ultra Low 190 A (typ) Quiescent Current
` 1 A Input Current During Standby
` Low Noise: 65 VRMS Without Bypass Capacitor
` Quick Output Capacitor Discharge Feature
` Two Manual Reset Inputs
` 2% Accuracy Over Load and Temperature
` Undervoltage Lockout (UVLO) Feature
` 20-Pin PowerPAD™ TSSOP Package
` Thermal Shutdown Protection
Pinout
SpecificationsInput voltage range‡: VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to 7 V
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Output voltage range (VOUT1, VSENSE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (VOUT2, VSENSE2) . . . . . . . . . . . . . . . . . . . . . .. . . . . . 5.5 V
Maximum RESET, PG1 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 V
Maximum MR1, MR2, and SEQ voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .VIN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . See Dissipation Rating Tables
Operating virtual junction temperature range, TJ . . . . . . . . . . . . .40 to 125
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and unctional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not mplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are tied to network ground.
DescriptionMR align=justify>TPS707xx family devices are designed to provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. Easy programmability of the sequencing function makes TPS707xx family ideal for any DSP applications with power sequencing requirement. Differentiated features, such as accuracy, fast transient response, SVS supervisory circuit (power on reset), manual reset inputs, and enable function, provide a complete system solution.
The TPS707xx family of voltage regulators offers very low dropout voltage and dual outputs with power up equence control, which is designed primarily for DSP applications. TPS707xx have extremely low noise utput performance without using any added filter bypass capacitors and are designed to have a fast transient esponse and be stable with 10 uF low ESR capacitors.
TPS707xx have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable/adjustable voltage ptions. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage nputs allow the designer to configure the source power.
Because the PMOS TPS707xx behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV n regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is voltage-driven TPS707xx, the quiescent current is very low and independent of output loading (maximum of 30 mA over the full range of output current). This LDO family also features a sleep mode; applying a high signal to EN(enable) shuts down both regulators, reducing the input current to 1 A at TJ = 25.
The TPS707xx is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two regulators are sensed at the VSENSE1 and VSENSE2 pins respectively.
The input signal of TPS707xx at the SEQ pin controls the power-up sequence of the two regulators. When the device is nabled and the SEQ terminal is pulled high or left open, VOUT2 will turn on first and VOUT1 will remain off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time VOUT1will be turned on. If VOUT2 s pulled below 83% (i.e. over load condition) VOUT1 will be turned off. Pulling the SEQ terminal low, reverses he power-up order and VOUT1 will be turned on first. The SEQ pin of TPS707xx is connected to an internal pullup current ource.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator s turned off(disabled).
The PG1 pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the ircuitry supplied by regulator 1.
The TPS707xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP ystems and related digital applications in the event of an undervoltage condition. RESET indicates the status f VOUT2 and both manual reset pins (MR1and MR2). When VOUT2 reaches 95% of its regulated voltage and MR1 and MR2 are in the logic high state, RESET will go to a high impedance state after 120 ms delay. RESET ill go to logic low state when VOUT2 regulated output voltage is pulled below 95% (i.e. over load condition) of ts regulated voltage. To monitor VOUT1 , the PG1 output pin can be connected to MR1 or MR2.
The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until IN1 reaches 2.5V.
TPS70758 Data Sheet
