TPS70402

Input voltage range‡: V_IN1 . . . . . . . . . . . . . . . . . . . . . . .  . . . 0.3 V to 7 V
                                     V_IN2 . . . . . . . . .. . . . . . . . . . . . . . . .  . 0.3 V to 7 V
Voltage range at EN1, EN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Output voltage range (V_OUT1, V_SENSE1) . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (V_OUT2, V_SENSE2) . . . . . . . . .  . . . . . . . . . . . . .  . 5.5 V
MaximumRESET, PG1, PG2 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 7 V
Maximum MR voltage . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . V_IN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . See Dissipation Rating Tables
Operating virtual junction temperature range, T_J . . . . . . . . . 40 to 150
Storage temperature range, T_stg . . . . . . . . . . . . . . . . . . . . . . 65to 150
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 2 kV

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.  hese are stress ratings only, and unctional operation of the device at these or any other conditions beyond those ndicated under "recommended operating conditions" is not mplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are tied to network ground.

The TPS70402 devices consists of ual-output low-dropout voltage regulators with ntegrated SVS (RESET, POR, or power on reset) nd power good (PG) functions. These TPS70402 are capable of supplying 1 A and 2 A by regulator  and regulator 2 respectively. Quiescent current s typically 185 A at full load. Differentiated eatures, such as accuracy, fast transient esponse, SVS supervisory circuit of TPS70402 (power on eset), manual reset input, and independent nable functions provide a complete system olution.

The TPS70402 voltage regulators offers very low dropout voltage and dual outputs. These devices ave extremely low noise output performance without using any added filter bypass capacitors and are esigned to have a fast transient response and be stable with 47 F low ESR capacitors.

These TPS70402 have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.Regulator 1 can support up to 1 A, and regulator 2 can support up to 2 A. Separate voltage inputs allow the esigner to configure the source power.

Because the PMOS pass element of TPS70402 behaves as a low-value resistor, the dropout voltage is very low (typically 160mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass elementis a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 50 A over the full range of output current and full range of temperature). This LDO family TPS70402 also features a sleep ode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When  high signal is applied to both EN1 and EN2, both regulators are in sleep mode, thereby reducing the input urrent to 2 A at T_J = 25°C.

For each regulator TPS70402, there is an internal discharge transistor to discharge the output capacitor when the regulator s turned off (disabled).

The PG1 pin of TPS70402 reports the voltage condition at V_OUT1. The PG1 pin can be used to implement a SVS (RESET, OR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions t V_OUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.

The TPS70402 features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output nd requires a pullup resistor for normal operation. When pulled up, RESET goes into a high impedance state i.e. logic high) after 120 ms delay when both of the following conditions are met. First, V_IN1 must be above the ndervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. To monitor V_OUT1, the PG1 output pin of TPS70402 can be connected to MR. To monitor V_OUT2, the PG2 output pin can be connected o MR. RESET can be used to drive power on reset or a low-battery indicator. If RESET is not used, it can be eft floating.