Features: * Power-On Reset Generator With Fixed Delay Time of 200 ms (TPS3823/4/5/8) or 25 ms (TPS3820)
* Manual Reset Input (TPS3820/3/5/8)
* Reset Output Available in Active-Low (TPS3820/3/4/5), Active-High (TPS3824) and Open-Drain (TPS3828)
* Supply Voltage Supervision Range 2.5 V, 3 V, 3.3 V, 5 V
* Watchdog Timer (TPS3820/3/4/8)
* Supply Current of 15 A (Typ)
* SOT23-5 Package
* Temperature Range . . . 40 to 85Application* Applications Using DSPs, Microcontrollers,or Microprocessors
* Industrial Equipment
* Programmable Controls
* Automotive Systems
* Portable/Battery-Powered Equipment
* Intelligent Instruments
* Wireless Communications Systems
* Notebook/Desktop ComputersPinout
SpecificationsSupply voltage, VDD (see Note 1). . . . . . . . . . . . . . . . . . . . . . . . 6 V
RESET, RESET, MR, WDI (see Note 1). . . . . 0.3 V to (VDD + 0.3 V)
Maximum low output current, IOL. . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, IOH. . . . . . . . . . . . . . . . . . . 5 mA
Input clamp current range, IIK (VI < 0 or VI > VDD). . . . . . ±10 mA
Output clamp current range, IOK (VO < 0 or VO > VDD). . . ±10 mA
Continuous total power dissipationSee Dissipation Rating Table
Operating free-air temperature range, TA. . . . . . . . .40 to 85
Storage temperature range, Tstg. . . . . . . . . . . . . . 65 to 150
Soldering temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
DescriptionThe TPS38208-xx family of supervisors provides circuit initialization and timing supervision,primarily for DSP and processor-based systems. During power-on, RESET is asserted when supply voltage VDD becomes higher than 1.1 V.Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage VIT.
An internal timer of TPS38208-xx delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage VIT. When the supply voltage drops below the threshold voltage VIT, the output becomes active (low) again. No external components are required. TPS38208-xx of this family have a fixed-sense threshold voltage VIT set by an internal voltage divider.
The TPS38208-xx devices incorporate a manual reset input, MR. A low level at MR causes RESET to become active. The TPS3824/5 devices include a high-level output RESET. TPS3820/3/4/8 have a watchdog timer that is periodically triggered by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval, ttout, RESET becomes active for the time period td. This event of TPS38208-xx also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog.
In applications where the input to the WDI pin may be active (transitioning high and low) when the TPS3820/3/4/8 is asserting RESET, the TPS38208-xx does not return to a non-reset state when the input voltage is above Vt. If the application requires that input to WDI is active when RESET is asserted, WDI must be decoupled from the active signal. This can be accomplished by using an N-channel FET in series with the WDI pin, with the gate of the FET connected to the RESET output as shown in Figure 1.
TPS38208-xx Data Sheet
