TPS3707-25

Features:

Power-On Reset Generator with Fixed Delay Time of 200 ms, no External Capcitor Needed
Precision Supply Voltage Monitor 2.5 V, 3 V,3.3 V, and 5 V
Pin-For-Pin Compatible with the MAX705 through MAX708 Series
Integrated Watchdog Timer (TPS3705 only)
Voltage Monitor for Power-Fail or Low-Battery Warning
Maximum Supply Current of 50 mA
MSOP-8 and SO-8 Packages
Temperature Range . . . 40°C to 85°C

Application

 Designs Using DSPs, Microcontrollers or Microprocessors
 Industrial Equipment
 Programmable Controls
 Automotive Systems
 Portable/Battery Powered Equipment
 Intelligent Instruments
 Wireless Communication Systems
 Notebook/Desktop Computers


Pinout




Specifications

Supply voltage, V_DD (see Note1) .. . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
All other pins (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Maximum low output current, I_OL . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Maximum high output current, I_OH . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Input clamp current, I_IK (V_I < 0 or V_I > V_DD) . . . . . . . . . . . . . . . ±20 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_DD)  . . . . . . . . . . . . ±20 mA
Continuous total power dissipation ... . . . . See Dissipation Rating Table
Operating free-air temperature range, T_A . . . . . . . . . . 40°C to 85°C
Storage temperature range, T_stg . . . . . . . . . . . . . . . . 65°C to 150°C
Soldering temperature . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . 260°C


Description

The TPS3705, TPS3707 family of microprocessor supply-voltage supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems.

During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor of  TPS3705, TPS3707  monitors VDD and keeps RESET active as long as VDD remains below the threshold voltage VIT+. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td typ = 200 ms, starts after VDDhas risen above the threshold voltage V_IT+. When the supply voltage drops below the threshold voltage V_IT , the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage V_IT set by an internal voltage divider.