TPS3124J18

Features:

Minimum Supply Voltage of 0.75 V
Supply Voltage Supervision Range:
-1.2 V, 1.5 V, 1.8 V (TPS3123, TPS3124,TPS3125)
- 3 V (TPS3125 Devices only)
Power-On Reset Generator With Fixed
Delay Time of 180 ms
Manual Reset Input (TPS3123 and TPS3125)
Watchdog Timer Retriggers the RESET Output at V_DD V_IT
Supply Current of 14 m A (Typ)
SOT235 Package
Temperature Range ...40 to 85


Application

Applications Using Low Voltage DSPs,Microcontrollers or Microprocessors
Wireless Communication Systems
Portable/Battery-Powered Equipment
Programmable Controls
Intelligent Instruments
Industrial Equipment
Notebook/Desktop Computers
Automotive Systems


Specifications

Supply voltage, V_DD (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .  3.6 V
All other pins (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.3 V to 3.6 V
Maximum low output current, I_OL  . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . 5 mA
Maximum high output current, I_OH  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -5 mA
Input clamp current, I_IK (V_I < 0 or V_I > V_DD )  . . . . . . . . . . . . . . . . . . . . .±10 mA
Output clamp current, I_OK (V_O < 0 or V_O  > V_DD )  . . . . . . . . . . . . . . . . .  ±10 mA
  Continuous total power dissipation  . . . . . . . . . . . . .See Dissipation Rating Table
Operating free-air temperature range, T_A 40. . . . . . . . . . . . . . . . .-40 to  85 
Storage temperature range, T_stg65. . . . . . . . . . . . . . . . . . . . . . . . -65 to 150
Soldering temperature  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  260


Description

The TPS3123, TPS3124, TPS3125 family of ultra-low voltage processor supervisory circuits provides circuit initialization and timing supervision, primarily for DSP and processor-based systems.

During power-on, RESET of TPS3123, TPS3124, TPS3125  is asserted when the supply voltage (V_DD) becomes higher than 0.75 V. Thereafter,the supply voltage supervisor monitors V_DD and keeps RESET output active as long as V_DD remains below the threshold voltage V_IT.  An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, t_dtyp= 180 ms starts after V_DD has risen above the threshold voltage V_IT .