TPIC6C596

Features: Low rDS(on) . . . 7 TypAvalanche Energy . . . 30 mJEight Power DMOS Transistor Outputs of 100-mA Continuous Current250-mA Current Limit CapabilityESD Protection . . . 2500 VOutput Clamp Voltage . . . 33 V Enhanced Cascading for Multiple Stages All Registers Cleared With Single InputLow ...

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SeekIC No. : 004526408 Detail

TPIC6C596: Features: Low rDS(on) . . . 7 TypAvalanche Energy . . . 30 mJEight Power DMOS Transistor Outputs of 100-mA Continuous Current250-mA Current Limit CapabilityESD Protection . . . 2500 VOutput Clamp V...

floor Price/Ceiling Price

Part Number:
TPIC6C596
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

 Low rDS(on) . . . 7 Typ
 Avalanche Energy . . . 30 mJ
 Eight Power DMOS Transistor Outputs of 100-mA Continuous Current
 250-mA Current Limit Capability
 ESD Protection . . . 2500 V
 Output Clamp Voltage . . . 33 V
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input

 Low Power Consumption
 


Pinout

  Connection Diagram




Specifications

Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Logic input voltage range, VI  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 7 V
Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .33 V
Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 250mA
Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . .  . . . .500mA
Pulsed drain current, each output, all outputs on, ID, TC = 25°C (see Note 3)  . . . . . . . . 250mA
Continuous drain current, each output, all outputs on, ID, TC= 25°C  . . . . . . . . . . . . . . .100 mA
Peak drain current single output, TC= 25°C (see Note 3)  . . . . . . . . . . . . . . . . . . . . . .  . . 250mA
Single-pulse avalanche energy, EAS (see Figure 4)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ
Avalanche current, IAS (see Note 4)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA
Continuous total dissipation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . 40°C to 150°C
Operating case temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40°C to 125°C
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . .  . . . 260°C



Description

The TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The TPIC6B596 device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other mediumcurrent or high-voltage loads.

This TPIC6B596 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR) is high. When SRCLR is low, all registers in the TPIC6B596 device are cleared. When output enable (G) is held high, all data in the
output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOStransistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.




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