PinoutSpecificationsDrain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . .60 VSource-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .100 V Drain-to-GND voltage (Q1, Q3) . ....
TPIC5424L: PinoutSpecificationsDrain-to-source voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .. . . . . . .60 VSource-to-GND voltage (Q1, Q3) . . . . . . . . . . . ....
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The TPIC5424L is a monolithic logic-level power DMOS array that consists of four electrically isolated N-channel enhancement-mode DMOS transistors, two of which are configured with a common source.
The TPIC5424L is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body surface-mount (DW) package. The TPIC5424L is characterized for operation over the case temperature range of 40°C to 125°C.