TP3410

Features: `2 `B'+`D' channel 160 kbps transceiver for LT and NT`Meets ANSI T1.601 U.S. Standard`2B1Q line coding with scrambler/descrambler`Range exceeds 18 kft of 26 AWG`>70 dB adaptive echo-cancellation and equalization`On-chip timing recovery, no precision external components`Direct connection ...

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SeekIC No. : 004525873 Detail

TP3410: Features: `2 `B'+`D' channel 160 kbps transceiver for LT and NT`Meets ANSI T1.601 U.S. Standard`2B1Q line coding with scrambler/descrambler`Range exceeds 18 kft of 26 AWG`>70 dB adaptive echo-cancel...

floor Price/Ceiling Price

Part Number:
TP3410
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

`2 `B'+`D' channel 160 kbps transceiver for LT and NT
`Meets ANSI T1.601 U.S. Standard
`2B1Q line coding with scrambler/descrambler
`Range exceeds 18 kft of 26 AWG
`>70 dB adaptive echo-cancellation and equalization
`On-chip timing recovery, no precision external components
`Direct connection to small line transformer
`Automatic activation controller
`Selectable digital interface formats:
` TDM with time-slot assigner up to 64 slots, plus MICROWIRETM control interface
` GCI (General Circuit Interface), or
` IDL (Inter-chip Digital Link)
`Backplane clock DPLL allows free-running XTAL
`Elastic data buffers meet Q.502 wander/jitter for Slaveslave mode on PBX Trunk Cards and DLC
`EOC and spare bits access with automatic validation
`Block error counter
`6 loopback test modes
`Single +5V supply, 325 mW active power
`20 mW idle mode with line signal ``wake-up'' detector



Application

· LT, NT-1, NT-2 Trunks, U-TE's, Regenerators etc.
· Digital Loop Carrier
· POTS Pair-Gain Sy stems
· Easy  Interface to:
-Line Card Backplanes
-``S'' Interface Device TP3420A
-Codec/Filter Combos TP3054/7 and TP3075/6
-LAPD Processor MC68302, HPC16400
-HDLC Controller TP3451



Pinout

  Connection Diagram


Specifications


If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
VCC to GND...................... 7V
Voltage at Li, Lo......... VCC + 1V to GND - 1V
Voltage at Any Digital Input ...VCC + 1V to GND -1V
Storage Temperature Range.... -65°C to +150°C
Current at Lo ..................±200  A
Current at Any Digital Output.......... ±50 mA
Lead Temperature (Soldering, 10 seconds).... 300°C
ESD (Human Body Model) J ..............TBD
JA (Package Number J28A)........... 40°C/W



Description

The TP3410 is a complete monolithic transceiver for ISDN Basic Access data transmission at either end of the U interface. Fully compatible with ANSI specification T1.601, TP3410 is built on National's advanced double-metal CMOS process, and requires only a single +5V power supply. A total of 160 kbps full-duplex transmission on a single twisted-pair is provided, with user-accessible channels including 2 `B' channels, each at 64 kbps, 1 `D' channel at 16 kbps, and an additional 4 kbps for loop maintenance. 12 kbps of bandwidth is reserved for framing. 2B1Q Line coding is used, in which pairs of binary bits are coded into 1 of 4 quantum levels for transmission at 80k symbols/sec (hence 2 Binary/ 1 Quaternary). To meet the very demanding specifications for< 1 in 10e7 Bit Error Rate even on long loops with crosstalk, the TP3410 device includes 2 Adaptive Digital Signal Processors, 2 Digital Phase-locked Loops and a controller for automatic activation.

The digital interface on the TP3410 device can be programmed for compatibility with either of two types of control interface for chip control and access to all spare bits. In one mode a Microwire serial control interface is used together with a 2B+D digital interface which is compatible with the Time-division Multiplexed format of PCM Combo devices and backplanes. This mode allows independent time-slot assignment for the 2 B channels and the D channel. Alternatively, the GCI (General Circuit Interface) may be selected, in which the 2B+D data is multiplexed together with control, spare bits and loop maintenance data on 4 pins.


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