TP0702N3

The TP0702N3 can be applicated in (1)logic level interface; (2)solid state relays; (3)battery operated systems; (4)photo voltarc dnve; (5)analog switches; (6)general purpose line driver; (7)telecom switches. These TP0702N3 low threshold enhancement-made (normally-oft) power transistors utilize a vertical DMOS structure and Supertex's well- proven silicon-gate manufacturing process. Supertex Vertical DMOS Power FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input imped- ance, low input capacitance, and fast switching speeds are desired. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input Impedance and positive temperature coefticlent inherent in MOS devices. Characteristic ot all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown.

The features of TP0702N3 can be summarized as (1)low threshold -1.0V max; (2)on resistance guaranteed at VGS = 2, 3, and 5 voits; (3)high input impedance; (4)low input capacitance -130 pF typical; (5)fast switching speeds; (6)low on resistance; (7)free from secondary breakdown; (8)low input and output leakage .

The absolute maximum ratings of TP0702N3 are (1)drain-to-source vottage: BVDSS; (2)drain-to-gate voltage: BVDGS; (3)gate-to-source voltage: 20V; (4)operating and storage temperature: -55°C to +150°C; (5)soldering temperature(distance of 16 mm from case for 10 seconds): 300°C.