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TNETA1570

Features: · Single-Chip Segmentation and Reassembly Device (SAR) for Full-Duplex ATM-Adaptation-Layer (AAL) Processing· Integrated 64-Bit Peripheral-Component Interface for Transferring Data and Control Information for Packet Segmentation and Packet Reassembly· Provides Complete Encapsulation and ...

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SeekIC No. : 004525459 Detail

TNETA1570: Features: · Single-Chip Segmentation and Reassembly Device (SAR) for Full-Duplex ATM-Adaptation-Layer (AAL) Processing· Integrated 64-Bit Peripheral-Component Interface for Transferring Data and Con...

TNETA1570 Data Sheet

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Part Number:
TNETA1570
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Single-Chip Segmentation and Reassembly
  Device (SAR) for Full-Duplex
  ATM-Adaptation-Layer (AAL) Processing
· Integrated 64-Bit Peripheral-Component
  Interface for Transferring Data and Control
  Information for Packet Segmentation and Packet Reassembly
· Provides Complete Encapsulation and Termination of AAL5 Packets
· Supports Both Transmit and Receive Buffer
  Chaining (Buffer Scatter/Gather)
· Provides for Early Segmentation of a Transmit Packet by Beginning the
  Segmentation Process Once a Transmit 
  Buffer Is Available Instead of Waiting for the Entire Packet to Be Buffered
· Provides Full VPI/VCI Support and Allows for the Simultaneous Segmentation of 1023 Packets and the Simultaneous
  Reassembly of 30720 Packets
· Byte-Wide Cell Interface Is Full Duplex and Compliant to the ATM-Forum UTOPIA Document
· Cell Interface Can Be Programmed to Operate as Either a Physical (PHY)-Layer
  Interface or as a ATM-Layer Interface
· Provides Reassembly Time-Out for an Incoming Packet
· Provides a High-Priority Mechanism for Transmitting Constant-Bit-Rate Traffic
· Provides Support for Transparent/Null AAL


Pinout

Connection Diagram


Specifications

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  0.5 V to VCC + 0.5 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 2) . . . . . .  . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 3) . . . . . . .. . . . . .. ±20 mA
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . .. . . .. . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . .. . . . . . . . . . 65°C to 150°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to the GND terminals.
             2. Applies for external input and bidirectional buffers
             3. Applies for external output and bidirectional buffers


Description

The TNETA1570 is an asynchronous transfer mode (ATM) segmentation and reassembly (SAR) device with a 64-bit peripheral component interconnect (PCI)-bus interface. This device incorporates ATM adaptation-layer (AAL) processing, ATM SAR processing for full-duplex operation up to STS-3c rate of 155.52 Mbit/s, and the controls for the register interface on the PHY layer. The device provides complet e
encapsulation and termination of AAL5 packets in hardware.
The TNETA1570 supports high-speed networking applications utilizing ATM protocols as either a backbone/backplane or desktop technology. Features include: high level of VPI/VCI support, high-priority segmentation option for constant-bit-rate traffic, early buffer segmentation, buffer scatter/gather capability, and 32-/64-bit PCI-bus support.

The TNETA1570 device contains an integrated 32-/64-bit PCI interface for transferring data and control information. The segmentation and reassembly processes use host memory for storing packets that are transmitted or received. No local-packet memory is required. The device is capable of segmenting up to 1023 packets simultaneously and reassembling 30720 packets simultaneously. The device supports the full range of VPI/VCI values for both transmit and receive operations.

The TNETA1570 also supports two methods of transporting a transparent/null AAL used for transferring proprietary information. In addition, the device recognizes ATM-layer OAM cells and provides a mechanism for handling these cells. The device contains a full-duplex, byte-wide cell interface compliant to the ATM-Forum UTOPIA specification. The cell interface can be programmed to operate as either a PHY-layer interface or a ATM-layer interface.

The integrated PCI-host interface operates as either a 32-bit or 64-bit interface for DMA operations. The device operates as a 64-bit interface if the target device can accept 64-bit transfers; otherwise, it operates as a 32-bit interface. The PCI-host interface provides both master and slave capability and operates at a frequency up to 33 MHz. The PCI-host interface is functionally compliant to the PCI-local-bus specification revision 2.0. The TNETA1570 operation is explained in detail in the Principles of Operation section.  




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