Features: Versatile IC supports 155/51 Mbits/s SONET/SDH interface solutions for T3/E3, DS2, T1/E1/J1, and DS0/E0/J0 applications.
Implementation supports both linear (1 + 1, unprotected) and ring (UPSR) network topologies.
Provides full termination of up to 21 E1, 28 T1, or 28 J1.
Low power 3.3 V supply.
40 °C to +85 °C industrial temperature range.
456-pin ball grid array (PBGA) package.
Complies with Bellcore*, ITU, ANSI †, ETSI and Japanese TTC standards: GR-253-CORE, GR-499, (ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,
G.962, G.964, G.965, Q.542, T1.105, JT-G704, JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1, ETS 300 011, T1.107, T1.404.
Application26 Applications .......................................................................................................................................... 587
26.1 Application Diagrams ......................................................................................................................... 588
26.2 High-Speed Line Interfaces and Clock and Data Recovery ................................................................ 589
26.2.1 Receive Direction ............................................................................................................................ 589
26.2.2 Transmit Direction ........................................................................................................................... 589
26.3 Multiplex Section Protection (MSP 1 + 1) ............................................................................................ 589
26.3.1 Pointer Interpreter .......................................................................................................................... 589
26.4 Path Termination Function .................................................................................................................. 590
26.5 STS-3/STM-1 MUX-DeMUX .................................................................................................................... 591
26.6 Telecom Bus Interface-Interfacing to Mate Devices ........................................................................... 591
26.7 SPE/AU-3 Mapper (DS3 Mapper) .......................................................................................................... 591
26.8 VT/VC Mapper ...................................................................................................................................... 592
26.8.1 Receive Direction .............................................................................................................................. 592
26.8.2 Transmit Direction ............................................................................................................................. 593
26.9 M13/M23 Multiplexer ............................................................................................................................ 593
26.9.1 Receive Direction ............................................................................................................................... 593
26.9.2 Transmit Direction .............................................................................................................................. 594
26.10 Cross Connect Block ........................................................................................................................... 594
26.11 Digital Jitter Attenuator ....................................................................................................................... 595
26.12 Test Pattern Generator ....................................................................................................................... 595
26.13 28-Channel Framer .............................................................................................................................. 596
26.14 Line Decoder/Encoder .......................................................................................................................... 601
26.15 Receive Frame Aligner/Transmit Frame Formatter ................................................................................ 601
26.16 Receive Performance Monitor ................................................................................................................ 601
26.17 Signaling Processor ............................................................................................................................... 602
26.18 Facility Data Link (FDL) Processor .......................................................................................................... 602
26.19 HDLC Unit ............................................................................................................................................... 603
26.20 System Interface......................................................................................................................................603
27 Change History ........................................................................................................................................... 604
Figures Page
Figure 102. Switching Application of the Super Mapper..................................................................................... 588
Figure 103. Transport Application of the Super Mapper..................................................................................... 588
Figure 104. Super Mapper Switching Mode for Framer in Concentration Highway
Interface (CHI) Configuration............................................................................................................................. 596
Figure 105. Super Mapper Switching Mode for Framer in Parallel System Bus Configuration ............................ 597
Figure 106. Super Mapper Switching Mode CHI Configuration with Byte-Synchronous VT Mapping Enabled .... 598
Figure 107. Super Mapper Byte-Synchronous Transport Mode: Passive Performance Monitoring...................... 599
Figure 108. Super Mapper Byte-Synchronous Transport Mode: Intrusive Performance Monitoring.................... 600
Tables Page
Table 628. Change History .................................................................................................................................604DescriptionTMXF28155 7 Microprocessor Interface and Global Control and Status Registers .................................................................. 62
7.1 Super Mapper Global Control and Status Registers ....................................................................................... 63
7.2 Microprocessor Interface Register Map .......................................................................................................... 73
Table 57. SMPR_VCR, Super Mapper Version Control Register (RO) ..................................................................... 63
Table 58. SMPR_SYMR[4], Super Mapper Symbol Register4 SMPR (RO) ................................................................ 63
Table 59. SMPR_SYMR[3], Super Mapper Symbol Register3 (RO) .......................................................................... 63
Table 60. SMPR_SYMR[2], Super Mapper Symbol Register2 (RO) .......................................................................... 63
Table 61. SMPR_SYMR[1], Super Mapper Symbol Register1 (RO) .......................................................................... 64
Table 62. SMPR_SYMR[0], Super Mapper Symbol Register0 (RO) .......................................................................... 64
Table 63. SMPR_ISR, Super Mapper Interrupt Status Register (RO) ...................................................................... 64
Table 64. SMPR_IMR, Super Mapper Interrupt Mask Register (RW) ....................................................................... 65
Table 65. SMPR_GTR, Global Trigger Register (RW) ............................................................................................... 66
Table 66. SMPR_MSRR, Block Software Reset Register (RW) ................................................................................. 66
Table 67. SMPR_GCR, Global Control Register (RW) .............................................................................................. 68
Table 68. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW) ........................................................................ 69
Table 69. SMPR_FCR, Framer Control Register (RW) ............................................................................................. 69
Table 70. SMPR_CLCR, CDR and LVDS Control Register (RW) ............................................................................... 70
Table 71. SMPR_CPCR, Clock and Power Control Register (RW) ........................................................................... 71
Table 72. SMPR_PMRCHR, PM Reset Count High Register (RW) ............................................................................. 71
Table 73. SMPR_PMRCLR, PM Reset Count Low Register (RW) .............................................................................. 72
Table 74. SMPR_SR, Scratch Register (RW) ............................................................................................................ 72
Table 75. SMPR_TX_LINE_EN1 ............................................................................................................................... 72
Table 76. Microprocessor Interface Register Map ................................................................................................... 73
TMXF28155 Data Sheet
