TMP320C50KGD

Features: 35-ns and 50-ns Single-Cycle Instruction Execution Time for 5 V Operation50-ns Single-Cycle Instruction Execution Time for 3.3 V OperationSource-Code Compatible With All 'C1x and 'C2x DevicesRAM-Based Operation 9K-Words * 16-Bit Single-Access On-Chip Program/Data RAM 1056-Word * 16-Bit...

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SeekIC No. : 004524389 Detail

TMP320C50KGD: Features: 35-ns and 50-ns Single-Cycle Instruction Execution Time for 5 V Operation50-ns Single-Cycle Instruction Execution Time for 3.3 V OperationSource-Code Compatible With All 'C1x and 'C2x Devi...

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Part Number:
TMP320C50KGD
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

35-ns and 50-ns Single-Cycle Instruction Execution Time for 5 V Operation
50-ns Single-Cycle Instruction Execution Time for 3.3 V Operation
Source-Code Compatible With All 'C1x and 'C2x Devices
RAM-Based Operation
   9K-Words * 16-Bit Single-Access On-Chip Program/Data RAM
   1056-Word * 16-Bit Dual-Access On-ChipData RAM
2K-Word * 16-Bit On-Chip Boot ROM
224K-Word * 16-Bit Maximum Addressable External Memory Space (64K-Word
   Program, 64K-Word Data, 64K-Word I/O, and 32K-Word Global)
32-Bit Arithmetic Logic Unit (ALU)
    32-Bit Accumulator (ACC)
    32-Bit Accumulator Buffer (ACCB)
16-Bit Parallel Logic Unit (PLU)
16 * 16-Bit Multiplier, 32-Bit Product
Eleven Context Switch Registers
Two Buffers for Circular Addressing
Full-Duplex Synchronous Serial Port
Time-Division Multiplexed Serial Port (TDM)
Timer With Control and Counter Registers
16 Software Programmable Wait-State Generators
Divide-By-1 Clock Option
IEEE Standard 1149.1† Test Access Port
Operations are Fully Static
Fabricated Using the Texas Instruments Enhanced Performance Implanted CMOS (EPICE) 0.72-mm Technology



Description

The TMP320C50KGD digital signal processor (DSP) is a high performance, 16-bit, fixed-point processor manufactured in 0.72-mm double-level metal CMOS technology. The TMP320LC50KGD has the same functionality as the 'C50KGD except for operation at 3.3 V instead of 5 V.

Texas Instruments Military Products TMP320C50KGD currently employs three primary processes for the development of a known good die (KGD), one of which is applied to the TMP320C50 and TMP320LC50 devices. This process, known as hot-chuck-probe, uses a standard probed product that is tested again, this time at full data sheet specifications, in wafer form at speed and elevated temperature (85°C). Each individual die then is sawed, inspected, and packed for shipment. This flow produces a bare die that has been temperature-tested at speed and is known to be good, without having to use a temporary package.

A number of enhancements to the basic 'C2x architecture give the 'C5x a minimum 2x performance over the previous generation. A four-deep instruction pipeline, incorporating delayed branching, delayed call to subroutine, and delayed return from subroutine, allows the 'C5x to perform instructions in fewer cycles. The addition of a PLU TMP320C50KGD gives the 'C5x a method of manipulating bits in data memory without using the accumulator and ALU. The 'C5x has additional shifting and scaling capability for proper alignment of multiplicands or storage of values to data memory.




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