TMP320C40KGDC

Features: 􀀀 Six communication ports for direct interprocessor communication and processor I/O􀀀 20 MBps bidirectional interface on each communication portfor high-speed and low-cost multiprocessor interface􀀀 Separate input and output first-in, first-out (FIFO) buffers fo...

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SeekIC No. : 004524387 Detail

TMP320C40KGDC: Features: 􀀀 Six communication ports for direct interprocessor communication and processor I/O􀀀 20 MBps bidirectional interface on each communication portfor high-speed and low-cost...

floor Price/Ceiling Price

Part Number:
TMP320C40KGDC
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/1/11

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Product Details

Description



Features:

􀀀 Six communication ports for direct interprocessor communication and processor I/O
􀀀 20 MBps bidirectional interface on each communication port
    for high-speed and low-cost multiprocessor interface
􀀀 Separate input and output first-in, first-out (FIFO) buffers
    for I/O and processor-to-processor communication
􀀀 Automatic arbitration and handshaking for direct processor-to-processor connection
􀀀 Link pointers that allow DMA channels to auto-initialize
􀀀 Parallel CPU operation and DMA transfers
􀀀 Six DMA channels support communication-port-to-memory data transfers



Description

The TMP/SMJ320C40KGD DSP is a 32-bit, floating-point processor manufactured in 0.72-mm, double-level metal CMOS technology. It is the fourth generation of DSPs from Texas Instruments, and it is the world's first DSP designed for parallel processing. The on-chip parallel processing capabilities of the 'C40 make the floating-point performance required by many applications achievable and cost-effective.

The TMP/SMJ320C40 is the first DSP with on-chip communication ports for processor-to-processor communication using simple communication software with no external hardware. This allows connectivity with no external glue logic. The communication ports remove I/O bottlenecks, and the independent smart-DMA coprocessor is able to handle the CPU I/O requirements.




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